DSPIC33FJ128GP710-I/PT Microchip Technology, DSPIC33FJ128GP710-I/PT Datasheet - Page 16
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DSPIC33FJ128GP710-I/PT
Manufacturer Part Number
DSPIC33FJ128GP710-I/PT
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
3.DSPIC33FJ64GP206-IPT.pdf
(28 pages)
4.DSPIC33FJ128MC506-IPT.pdf
(24 pages)
Specifications of DSPIC33FJ128GP710-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP710-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
30. Module: SPI
31. Module: UART
DS80446D-page 16
SPI1 functionality for pin 34 (U1RX/SDI1/RF2) is
enabled by the SPI2 module. As a result, two side
effects occur:
1. RF2 functionality is disabled if the SPI2 module
2. This pin will not function as SDI1 if the SPI1
This issue affects 64-pin devices only:
• dsPIC33FJ64GP206
• dsPIC33FJ128GP206
• dsPIC33FJ64GP306
• dsPIC33FJ128GP306
• dsPIC33FJ256GP506
• dsPIC33FJ64GP706
• dsPIC33FJ128GP706
Work around
Two conditions apply:
1. If the SPI2 module is used, pin 34 cannot be
2. If the SPI1 module is used, the SPI2 module
Affected Silicon Revisions
The auto-baud feature may miscalculate for
certain baud rate and clock speed combinations,
resulting in a BRG value that is greater than or less
than the expected value by 1. This may result in
reception or transmission failures.
Work around
Test the auto-baud rate at various clock speed and
baud rate combinations that would be used in an
application. If an inaccurate BRG value is
generated, manually correct the baud rate in the
user software.
Affected Silicon Revisions
A2
A2
X
X
is enabled.
module is enabled.
used as an I/O (RF2). It is recommended to
use another I/O pin.
must also be enabled to gain SDI1 functionality
on pin 34. As an alternative, I/O (RF2) can be
configured as an input, which will allow pin 34
to function as SDI1.
A3
A3
X
X
A4
A4
X
X
32. Module: Device ID Register
On a few devices, the content of the Device ID
register can change from the factory programmed
default value immediately after RTSP or ICSP™
Flash programming.
As a result, development tools will not recognize
these devices and will generate an error message
indicating that the device ID and the device part
number
peripherals will be reconfigured and will not
function as described in the device data sheet.
Refer to Section 5. “Flash Programming”
(DS70191), of the “dsPIC33F Family Reference
Manual” for an explanation of RTSP and ICSP
Flash programming.
Work around
All RTSP and ICSP Flash programming routines
(excluding Configuration Memory programming
routines) must be modified as follows:
1. No word programming is allowed. Any word
2. During row programming, load write latches as
3. After latches are loaded, reload any latch
4. Start
5. After row programming is complete, verify the
6. If Flash verification errors are found, repeat
Steps 1 through 5 in the work around are
implemented in MPLAB IDE version 8.00 or higher
for the MPLAB ICD 2, MPLAB REAL ICE™ in-circuit
emulator and PM3 tools.
Affected Silicon Revisions
A2
X
programming must be replaced with row
programming.
described in 5.4.2.3 “Loading Write Latches”
of
(DS70191).
location (in a given row) that has 5 LSB set to
0x18, with the original data. For example,
reload one of the following latch locations with
the desired data:
0xXXXX18, 0xXXXX38, 0xXXXX58,
0xXXXX78, 0xXXXX98, 0xXXXXB8,
0xXXXXD8, 0xXXXXF8
NVMOP<3:0> = ‘0001’ (memory row program
operation) in the NVMCON register.
contents of Flash memory.
steps 2 through 5. If Flash verification errors
are found after a second iteration, report this
problem to Microchip.
A3
Section
X
do
row
A4
X
not
5.
© 2010 Microchip Technology Inc.
programming
match.
“Flash
Additionally,
Programming”
by
setting
some