PIC32MX360F256L-80I/PT Microchip Technology, PIC32MX360F256L-80I/PT Datasheet - Page 101
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PIC32MX360F256L-80I/PT
Manufacturer Part Number
PIC32MX360F256L-80I/PT
Description
IC PIC MCU FLASH 256K 100-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F032H-40IPT.pdf
(626 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX360F256L-80I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
100-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX3xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5 x 16 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
No. Of I/o's
85
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
6
Embedded Interface Type
EUART, I2C, PSP, SPI
No. Of Pwm Channels
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX360F256L-80I/PT
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC32MX360F256L-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX360F256L-80I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
12.0
FIGURE 12-1:
© 2010 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
Legend:
Note:
2: Some registers and associated bits
I/O PORTS
PIO Module
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS61120) of the “PIC32MX Family
Reference Manual”, which is available
from
(www.microchip.com/PIC32).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
WR PORT
R = Peripheral input buffer types may vary. Refer to Table 1-1 “Pinout I/O Descriptions” for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
WR TRIS
RD PORT
WR ODC
Peripheral Input
Data Bus
RD ODC
RD TRIS
SYS
WR LAT
SYS
RD LAT
Sleep
CLK
CLK
the
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Microchip
Peripheral Input Buffer
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Peripheral Module
web
D
D
D
CK
CK
CK
EN Q
EN Q
EN Q
R
site
Q
Q
Q
ODC
TRIS
LAT
1
0
Q
Output Multiplexers
Q
General purpose I/O pins are the simplest of peripher-
als. They allow the PIC
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
Following are some of the key features of this module:
• Individual Output Pin Open-drain Enable/Disable
• Individual Input Pin Weak Pull-up Enable/Disable
• Monitor Selective Inputs and Generate Interrupt
• Operation during CPU Sleep and Idle modes
• Fast Bit Manipulation using CLR, SET and INV
Figure 12-1 illustrates a block diagram of a typical
multiplexed I/O port.
Synchronization
CK
when Change in Pin State is Detected
Registers
D
1
0
1
0
PIC32MX3XX/4XX
Q
Q
CK
D
0
1
®
MCU to monitor and control
I/O Cell
DS61143G - page 101
I/O Pin