PIC32MX360F256L-80I/PT Microchip Technology, PIC32MX360F256L-80I/PT Datasheet - Page 351

• Manufacturer Part Number: PIC32MX360F256L-80I/PT
• Description: IC PIC MCU FLASH 256K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F256L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 256KB (256K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The following steps should be performed to properly
configure the timer peripheral for Synchronous Counter
mode operation:
1.
2.
3.
4.
5.
6.
7.
EXAMPLE 14-2:
14.3.4
In this mode, the timer clock source can only be the
internal
(TxCON<1>) = 0. The TxCK pin provides the gating
mechanism to enable and disable the timer counting,
TGATE (TxCON<7>) = 1. The 16-bit TMRx Count reg-
ister is enabled on the rising edge of the TxCK pin and
increments on every internal PBCLK cycle when the
timer clock prescale <TCKPS> is 1:1.
The timer increments until the TMRx Count register
matches the PRx register value. The TMRx Count reg-
ister resets to 0x0000 on the next PBCLK clock cycle.
A timer match event is not generated. The timer con-
tinues to increment and repeat the period match until
the falling edge of the TxCK pin or the timer is disabled.
On the falling edge of the gate signal, a timer gate
event is generated and the TMRx Count register stops
counting, but is not reset to 0x0000. The TMRx Count
register must be reset in software. For further details
regarding
Section 14.4 Timer Interrupts.
© 2008 Microchip Technology Inc.
T3CON = 0x0;
T3CONSET = 0x0072; //Prescaler=1:256,
TMR3 = 0x0;
PR3 = 0x3FFF;
T3CONSET = 0x8000;//Start Timer
Note:
Clear control bit,
disable timer.
Select the desired timer prescaler using bits,
TCKPS<2:0> (TxCON<6:4).
Set control bit, TCS (TxCON<1>) = 1, to select
an external clock source.
Clear Timer register, TMRx.
Load Period register, PRx, with desired 16-bit
match value.
If timer interrupts are used, refer to Section 14.4
Timer Interrupts for interrupt configuration
steps.
Set control bit, ON (TxCON<15>) = 1, to enable
timer.
PBCLK
SYNCHRONOUS INTERNAL 16-BIT
GATED TIMER
TxCK pins not available on 64-pin
devices..
timer
(Peripheral
events
SYNCHRONOUS
EXTERNAL 16-BIT TIMER
INITIALIZATION
ON (TxCON<15>) = 0, to
//Stop and Init Timer
//external clock
//Clear timer register
//Load period register
and
Bus
interrupts,
Clock),
Advance Information
TCS
see
For clock prescale = N (other than 1:1), the timer oper-
ates at a clock rate = (PBCLK/N); therefore, the TMRx
Count register increments on every Nth PBCLK clock
cycle.
refer to Section 14.3.9 Timer Clock Prescaler.
The following steps should be performed to properly
configure the timer peripheral for Gated Timer mode
operation:
1.
2.
3.
4.
5.
6.
7.
8.
EXAMPLE 14-3:
14.3.5
In this mode, T32 (TxCON<3>) = 1 and the timer clock
source is the internal PBCLK (Peripheral Bus Clock),
TCS (TxCON<1>) = 0. The 32-bit TMRxy Count regis-
ter increments on every internal PBCLK cycle when the
timer clock prescale <TCKPS> is 1:1.
The timer generates a timer match event after the
TMRxy Count register matches the PRxy Period regis-
ter value, then resets to 0x00000000 on the next
PBCLK clock cycle. The timer continues to increment
and repeat the period match until the timer is disabled.
For further details regarding timer events and
interrupts, see Section 14.4 Timer Interrupts.
T4CON = 0x0;
T4CON = 0x00E0;
TMR4 = 0;
PR4 = 0xFFFF;
T4CONSET = 0x8000;//Start Timer
Clear control bit, ON (TxCON<15>) = 0, to
disable Timer.
Select the desired timer prescaler using bits,
TCKPS<2:0> (TxCON<6:4>).
Set control bit, TCS (TxCON<1>) = 0, to select
the internal clock source.
Set control bit, TGATE (TxCON<7>) = 1.
Clear Timer register, TMRx.
Load Period register, PRx, with desired 16-bit
match value.
If timer interrupts are to be used, refer to
Section 14.4 Timer Interrupts for interrupt
configuration steps.
Set control bit, ON (TxCON<15>) = 1, to enable
timer.
PIC32MX FAMILY
For further details regarding timer prescaler,
SYNCHRONOUS INTERNAL 32-BIT
TIMER
SYNCHRONOUS
INTERNAL 16-BIT GATED
TIMER INITIALIZATION
//Stop and Init Timer
//Enable gated mode,
//prescaler=1:64,
//internal clock
//Clear timer register
//Load period register
DS61143B-page 349