DSPIC33FJ32GS610-I/PT Microchip Technology, DSPIC33FJ32GS610-I/PT Datasheet - Page 405
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DSPIC33FJ32GS610-I/PT
Manufacturer Part Number
DSPIC33FJ32GS610-I/PT
Description
IC MCU/DSP 32KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ32GS610-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Core Frequency
40MHz
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
85
Flash Memory Size
32KB
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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TABLE B-1:
2010 Microchip Technology Inc.
Section 9.0 “Oscillator Configuration” Removed Section 9.2 “FRC Tuning”.
Section 10.0 “Power-Saving Features” Updated the last paragraph of Section 10.2.2 “Idle Mode” to clarify when
Section 11.0 “I/O Ports”
Section 16.0 “High-Speed PWM”
Section 20.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Section 22.0 “High-Speed 10-bit
Analog-to-Digital Converter (ADC)”
Section 24.0 “Special Features”
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Section Name
MAJOR SECTION UPDATES (CONTINUED)
Removed the PRCDEN, TSEQEN, and LPOSCEN bits from the Oscillator
Control Register (see Register 9-1).
Updated the Oscillator Tuning Register (see Register 9-4).
Removed the Oscillator Tuning Register 2 and the Linear Feedback Shift
Register.
Updated the default reset values from R/W-0 to R/W-1 for the SELACLK
and APSTSCLR<2:0> bits in the ACLKCON register (see Register 9-5).
Renamed the ROSIDL bit to ROSSLP in the REFOCON register (see
Register 9-6).
instruction execution begins.
Added Note 1 to the PMD1 register (see Register 10-1).
Changed the reference to digital-only pins to 5V tolerant pins in the
second paragraph of Section 11.2 “Open-Drain Configuration”.
Updated the High-Speed PWM Module Register Interconnect Diagram
(see Figure 16-2).
Updated the SYNCSRC<2:0> = 111, 101, and 100 definitions to
Reserved in the PTCON and STCON registers (see Register 16-1 and
Register 16-5).
Updated the PWM time base maximum value from 0xFFFB to 0xFFF8 in
the PTPER register (Register 16-3).
Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 1
of the shaded note that follows the MDC register (see Register 16-10).
Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 2
of the shaded note that follows the PDCx and SDCx registers (see
Register 16-12 and Register 16-13).
Added Note 2 and updated the FLTDAT<1:0> and CLDAT<1:0> bits,
changing the word ‘data’ to ‘state’ in the IOCONx register (see
Register 16-19).
Updated the two baud rate range features to: 10 Mbps to 38 bps at 40
MIPS.
Updated the TRGSRCx<4:0> = 01101 definition from Reserved to PWM
secondary special event trigger selected, and updated Note 1 in the
ADCP0-ADCP6 registers (see Register 22-6 through Register 22-12).
Updated the second paragraph and removed the fourth paragraph in
Section 24.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 24-1).
Preliminary
Update Description
DS70591C-page 405
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