DSPIC33FJ32GS610-I/PT Microchip Technology, DSPIC33FJ32GS610-I/PT Datasheet - Page 182
![IC MCU/DSP 32KB FLASH 100TQFP](/photos/28/60/286070/100-tqfp-pt_sml.jpg)
DSPIC33FJ32GS610-I/PT
Manufacturer Part Number
DSPIC33FJ32GS610-I/PT
Description
IC MCU/DSP 32KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ32GS610-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Core Frequency
40MHz
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
85
Flash Memory Size
32KB
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Quantity
Price
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Part Number:
DSPIC33FJ32GS610-I/PT
Manufacturer:
Microchip
Quantity:
387
Company:
Part Number:
DSPIC33FJ32GS610-I/PT
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
DSPIC33FJ32GS610-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 182 of 418
- Download datasheet (3Mb)
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 8-5:
REGISTER 8-6:
DS70591C-page 182
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9-0
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
R/W-0
R/W-0
R/W-0
U-0
—
2: See Table 8-1 for a complete list of peripheral addresses.
2: Number of DMA transfers = CNT<9:0> + 1.
DMA channel and should be avoided.
DMA channel and should be avoided.
PAD<15:0>: Peripheral Address Register bits
Unimplemented: Read as ‘0’
CNT<9:0>: DMA Transfer Count Register bits
R/W-0
R/W-0
R/W-0
U-0
—
DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER
DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
Preliminary
—
PAD<15:8>
PAD<7:0>
CNT<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
(1)
CNT<9:8>
(1)
R/W-0
R/W-0
R/W-0
(2)
R/W-0
bit 8
bit 0
bit 8
bit 0
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