PIC24HJ64GP510-I/PF Microchip Technology, PIC24HJ64GP510-I/PF Datasheet - Page 6

• Manufacturer Part Number: PIC24HJ64GP510-I/PF
• Description: IC PIC MCU FLASH 32KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP510-I/PF

• Core Size: 16-Bit
• Program Memory Size: 64KB (22K x 24)
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 8KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• No. Of Pwm Channels: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24HJXXXGPX06/X08/X10
Silicon Errata Issues
1. Module: Doze Mode
DS80444D-page 6
Note:
Enabling Doze mode slows down the CPU, but
allows peripherals to run at full speed. When the
CPU clock is slowed down by enabling Doze mode
(CLKDIV<11> = 1), any writes to a peripheral SFR
can cause other updates to that register to cease
to function for the duration of the current CPU
clock cycle. This is only an issue if the CPU
attempts to write to the same register as a
peripheral while in Doze mode.
For instance, if the ADC module is active and Doze
mode is enabled, the main program should avoid
writing to ADCCONx registers because these
registers are being used by the ADC module. If the
CPU does make writes before the ADC module
does, then any attempts by the ADC module to
write to these registers will fail.
Work around
In Doze mode, avoid writing code that will modify
SFRs that may be written to by enabled
peripherals.
Affected Silicon Revisions
A2
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
A3
X
A4
X
© 2010 Microchip Technology Inc.