PIC24HJ64GP510-I/PF Microchip Technology, PIC24HJ64GP510-I/PF Datasheet - Page 22

• Manufacturer Part Number: PIC24HJ64GP510-I/PF
• Description: IC PIC MCU FLASH 32KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP510-I/PF

• Core Size: 16-Bit
• Program Memory Size: 64KB (22K x 24)
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 8KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• No. Of Pwm Channels: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24HJXXXGPX06/X08/X10
58. Module: I/O
59. Module: SPI
60. Module: ADC
DS80444D-page 22
While the device is being programmed via the
PGECx/PGEDx pin pair, the device pin with SDO1
functionality may start toggling.
Work around
None.
Affected Silicon Revisions
Regardless of the Slave setting for the Frame
delay bit (FRMDLY = 0 or FRMDLY = 1), the Slave
always acts as if the sync pulse precedes the first
SPI data bit (FRMDLY = 0). The SPI will not
function as described if Slave FRMDLY = 1.
Work around
None.
Affected Silicon Revisions
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV
instruction.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
PD
) may exceed the specifications listed
A4
A4
A4
X
X
X
PD
specifications
#0
© 2010 Microchip Technology Inc.