PIC18F4320-I/P Microchip Technology, PIC18F4320-I/P Datasheet - Page 185

• Manufacturer Part Number: PIC18F4320-I/P
• Description: IC MCU FLASH 4KX16 A/D 40-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/P

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.4.8
To initiate a Start condition, the user sets the Start
Condition Enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the Baud Rate Gener-
ator is reloaded with the contents of SSPADD<6:0>
and starts its count. If SCL and SDA are both sampled
high when the Baud Rate Generator times out (T
the SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the Start condition and
causes the S bit (SSPSTAT<3>) to be set. Following
this, the Baud Rate Generator is reloaded with the con-
tents of SSPADD<6:0> and resumes its count. When
the Baud Rate Generator times out (T
(SSPCON2<0>) will be automatically cleared by
hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
FIGURE 17-19:
© 2007 Microchip Technology Inc.
Note:
I
CONDITION TIMING
If, at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I
2
2
C module is reset into its Idle state.
C MASTER MODE START
Write to SEN bit occurs here
FIRST START BIT TIMING
SDA
SCL
BRG
), the SEN bit
PIC18F2220/2320/4220/4320
SDA = 1,
SCL = 1
T
BRG
BRG
),
Set S bit (SSPSTAT<3>)
T
S
BRG
At completion of Start bit,
hardware clears SEN bit
17.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
and sets SSPIF bit
Note:
T
Write to SSPBUF occurs here
BRG
1st bit
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
WCOL Status Flag
T
BRG
2nd bit
DS39599G-page 183