PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 11

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.2
Programming code memory is accomplished by first
loading data into the write buffer and then initiating a
programming sequence. The write buffer for all devices
in the PIC18F97J60 family is 64 bytes; it can be
mapped to any integral boundary of 64 bytes,
beginning at 000000h. The actual memory write
sequence takes the contents of this buffer and
programs the 64 bytes of code memory that contains
the Table Pointer.
Write buffer locations are not cleared following a write
operation; the buffer retains its data after the write is
complete. This means that the buffer must be written
with 64 bytes on each operation. If there are locations
in the code memory that are to remain empty, the
corresponding locations in the buffer must be filled with
FFFFh. This avoids rewriting old data from the previous
cycle.
The programming duration is internally timed. After a
Start Programming command is issued (4-bit com-
mand, ‘1111’), a NOP is issued, where the 4th PGC is
held high for the duration of the programming time, P9.
TABLE 3-3:
© 2009 Microchip Technology Inc.
Step 1: Enable writes.
Step 2: Load write buffer.
Step 3: Repeat for all but the last two bytes. Any unused locations should be filled with FFFFh.
Step 4: Load write buffer for last two bytes.
To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented by 2 at each iteration of the loop.
Command
0000
0000
0000
0000
0000
0000
0000
1101
1111
0000
4-Bit
Code Memory Programming
84 A6
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
<MSB><LSB>
<MSB><LSB>
00 00
WRITE CODE MEMORY CODE SEQUENCE
Data Payload
BSF
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2.
Write 2 bytes and start programming.
NOP - hold PGC high for time P9.
EECON1, WREN
PIC18F97J60 FAMILY
The code sequence to program a PIC18F97J60 family
device is shown in Table 3-3. The flowchart shown in
Figure 3-5 depicts the logic necessary to completely
write a PIC18F97J60 family device. The timing diagram
that details the Start Programming command and
parameter P9 is shown in Figure 3-6.
Note 1: To maintain the endurance specification
Core Instruction
2: The TBLPTR register must point to the
of the Flash program memory cells, each
64-byte block of program memory should
never be programmed more than once
between erase operations. If any byte
within a 64-byte block of program
memory is written, that entire block must
not be written to again until a Bulk Erase
on the part, or a Row Erase on the row
containing the modified 64-byte block,
has been performed.
same region when initiating the program-
ming sequence as it did when the write
buffers were loaded.
DS39688D-page 11