PIC18LF2439-I/SO Microchip Technology, PIC18LF2439-I/SO Datasheet - Page 208

• Manufacturer Part Number: PIC18LF2439-I/SO
• Description: IC MCU FLASH 6KX16 EE A/D 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2439-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 640 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 640 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIC18FXX39
FIGURE 20-2:
20.4
The overall structure of the code protection on the
PIC18 FLASH devices differs significantly from other
PICmicro devices. The user program memory is
divided on binary boundaries into individual blocks,
each of which has three separate code protection bits
associated with it:
• Code Protect bit (CPn)
• Write Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
The code protection bits are located in Configuration
Registers 5L through 7H. Their locations within the
registers are summarized in Table 20-3.
In the PIC18FXX39 family, program memory is divided
into segments of 8 Kbytes. The first block in turn
divided into a boot block of 512 bytes and a separately
protected remainder (Block 0) of 7.5 Kbytes. This
means for PIC18FXX39 devices, that there may be up
to five blocks, depending on the program memory size.
The organization of the blocks and their associated
code protection bits are shown in Figure 20-3.
DS30485A-page 206
(INTCON<1>)
(INTCON<7>)
Note
INSTRUCTION FLOW
Instruction
Instruction
INTF Flag
Executed
GIEH bit
CLKO
Fetched
INT pin
OSC1
1:
2:
3:
4:
Program Verification and
Code Protection
PC
(4)
XT, HS or LP Oscillator mode assumed.
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
T
CLKO is not available in these Osc modes, but shown here for timing reference.
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC - 1)
= 1024 T
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
(drawing not to scale). This delay will not occur for RC and EC Osc modes.
Inst(PC + 2)
PC+2
SLEEP
Processor in
SLEEP
PC+4
Preliminary
T
OST (2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 4)
Inst(PC + 2)
For PIC18FX439 devices, program memory is divided
into three blocks: a boot block, Block 0 (7.5 Kbytes)
and Block 1 (8 Kbytes). Block 1 is further divided in
half; the upper portion above 3000h is reserved, and
unavailable to user applications. The entire block can
be protected as a whole by bits CP1, WRT1 and
EBTR1. By default, Block 1 is not code protected.
For PIC18FX539 devices, program memory is divided
into five blocks: the boot block, Block 0 (7.5 Kbytes),
and Blocks 1 through 3 (8 Kbytes). Code protection is
implemented for the boot block and Blocks 0 through 2.
There is no provision for code protection for Block 3.
PC+4
Note:
Interrupt Latency
Dummy Cycle
The reserved segments of the program
memory space are used by the Motor Con-
trol kernel. For the kernel to function prop-
erly, this area must not be write protected.
If users are developing applications that
require code protection for PIC18FX439
devices, they should restrict program code
(or at least those sections requiring protec-
tion)
boundary.
PC + 4
(1,2)
to
below
(3)
 2002 Microchip Technology Inc.
Dummy Cycle
Inst(0008h)
0008h
the
1FFFh
Inst(000Ah)
Inst(0008h)
000Ah
memory