PIC18LF2439-I/SO Microchip Technology, PIC18LF2439-I/SO Datasheet - Page 126

• Manufacturer Part Number: PIC18LF2439-I/SO
• Description: IC MCU FLASH 6KX16 EE A/D 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2439-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 640 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 640 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIC18FXX39
15.1.2
The PWM duty cycle is set by the Motor Control module
when it writes a 10-bit value to the CCPR1L and
CCP1CON registers, where CCPR1L contains the
eight Most Significant bits and CCP1CON<5:4> con-
tains the two Least Significant bits. The duty cycle time
is given by the equation:
where T
time.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This buffer-
ing is essential for glitchless PWM operation. At the
same time, the value of TMR2 is concatenated with
TABLE 15-1:
DS30485A-page 124
INTCON
PIR1
PIE1
IPR1
TMR2
PR2
T2CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
Legend:
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
Name
PWM duty cycle = (10-bit CCP register value) •
*
*
*
*
OSC
*
*
*
*
*
x = unknown, u = unchanged, - = unimplemented, read as '0' unless otherwise noted. Shaded cells are not used by PWM
and Timer2.
These registers are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are reserved in
PIC18FXX39 devices. Users should not alter the values of these bits.
PWM DUTY CYCLE
and the duty cycle are in the same unit of
PWM Register1 (MSB) (read-only)
PWM Register2 (MSB) (read-only)
GIE/GIEH PEIE/GIEL
PSPIE
PSPIP
PSPIF
Bit 7
—
—
*
*
*
*
*
REGISTERS ASSOCIATED WITH PWM AND TIMER2
(1)
(1)
(1)
T
OSC
ADIF
ADIE
ADIP
Bit 6
—
—
*
*
*
*
*
• (TMR2 prescale value)
TMR0IE
RCIE
RCIP
RCIF
Bit 5
*
*
*
*
*
*
*
INT0IE
Bit 4
TXIF
TXIE
TXIP
*
*
*
*
*
*
*
Preliminary
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
*
*
*
*
*
*
*
either an internal 2-bit Q clock, or 2 bits of the TMR2
prescaler. When the CCPR1H:latch pair value matches
that of the TMR2:latch pair, the PWM1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
where F
Note:
TMR0IF
Bit 2
PWM Resolution (max)
—
—
—
*
*
*
*
*
*
*
PWM
If the PWM duty cycle value is longer than
the PWM period, the PWM1 pin will not be
cleared.
TMR2IE
TMR2IP
TMR2IF
is the PWM frequency, or (1/PWM period).
INT0IF
Bit 1
*
*
*
*
*
*
*
TMR1IE 0000 0000 0000 0000
TMR1IP 0000 0000 0000 0000
TMR1IF 0000 0000 0000 0000
 2002 Microchip Technology Inc.
RBIF
Bit 0
*
*
*
*
*
*
*
=
log
-----------------------------bits
0000 000x 0000 000u
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
POR, BOR
log


Value on
---------------
F
F
PWM
2 ( )
OSC


All Other
Value on
RESETS