ATMEGA324P-20PU Atmel, ATMEGA324P-20PU Datasheet - Page 224

IC MCU AVR 32K FLASH 40-DIP

ATMEGA324P-20PU

Manufacturer Part Number
ATMEGA324P-20PU
Description
IC MCU AVR 32K FLASH 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA324P-20PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire/JTAG/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Data Rom Size
1 KB
Height
4.83 mm
Length
52.58 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
13.97 mm
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
18.7.3
8011O–AVR–07/10
Slave Receiver Mode
Figure 18-14. Formats and States in the Master Receiver Mode
In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter
(see
are zero or are masked to zero.
Figure 18-15. Data transfer in Slave Receiver mode
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR
value
Successfull
reception
from a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
Figure
18-15). All the status codes mentioned in this section assume that the prescaler bits
SDA
SCL
From master to slave
From slave to master
$08
S
TWA6
SLA
Device 1
RECEIVER
SLAVE
R
TWA5
MR
TRANSMITTER
A or A
Device 2
DATA
$40
$48
$38
$68
MASTER
A
A
A
$78
TWA4
Other master
Other master
n
continues
continues
Device’s Own Slave Address
P
$B0
DATA
Device 3
A
TWA3
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
ATmega164P/324P/644P
........
$50
$38
To corresponding
states in slave mode
A
A
TWA2
Device n
Other master
DATA
continues
V
CC
$58
A
TWA1
R1
$10
R
P
S
R2
TWA0
SLA
W
R
TWGCE
MT
224

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