DSPIC30F4013-20I/ML Microchip Technology, DSPIC30F4013-20I/ML Datasheet - Page 220
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DSPIC30F4013-20I/ML
Manufacturer Part Number
DSPIC30F4013-20I/ML
Description
IC DSPIC MCU/DSP 48K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3014-30IPT.pdf
(228 pages)
2.DSPIC30F3014-30IPT.pdf
(16 pages)
3.DSPIC30F3014-30IPT.pdf
(6 pages)
4.DSPIC30F3014-30IPT.pdf
(14 pages)
5.DSPIC30F3014-30IPT.pdf
(20 pages)
6.DSPIC30F3014-20IP.pdf
(226 pages)
Specifications of DSPIC30F4013-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
48KB
Supply Voltage Range
2.5V To 5.5V
Package
44QFN EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
30
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
13-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F401320IML
dsPIC30F3014/4013
Data Address Space ........................................................... 30
Data Converter Interface (DCI) Module ............................ 121
Data EEPROM Memory ...................................................... 49
DC Characteristics ............................................................ 172
DCI Module
DS70138G-page 220
Round Logic ................................................................ 22
Write-Back .................................................................. 22
Alignment .................................................................... 32
Alignment (Figure) ...................................................... 32
Effect of Invalid Memory Accesses (Table)................. 32
MCU and DSP (MAC Class) Instructions Example..... 31
Memory Map ............................................................... 30
Near Data Space ........................................................ 33
Software Stack ............................................................ 33
Spaces ........................................................................ 32
Width ........................................................................... 32
Erasing ........................................................................ 50
Erasing, Block ............................................................. 50
Erasing, Word ............................................................. 50
Protection Against Spurious Write .............................. 52
Reading....................................................................... 49
Write Verify ................................................................. 52
Writing ......................................................................... 51
Writing, Block .............................................................. 51
Writing, Word .............................................................. 51
BOR .......................................................................... 180
I/O Pin Input Specifications ....................................... 178
I/O Pin Output Specifications .................................... 178
Idle Current (I
LVDL ......................................................................... 179
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 180
Temperature and Voltage Specifications .................. 172
Bit Clock Generator................................................... 125
Buffer Alignment with Data Frames .......................... 127
Buffer Control ............................................................ 121
Buffer Data Alignment ............................................... 121
Buffer Length Control ................................................ 127
COFS Pin .................................................................. 121
CSCK Pin .................................................................. 121
CSDI Pin ................................................................... 121
CSDO Mode Bit ........................................................ 128
CSDO Pin ................................................................. 121
Data Justification Control Bit ..................................... 126
Device Frequencies for Common Codec CSCK Frequen-
Digital Loopback Mode ............................................. 128
Enable ....................................................................... 123
Frame Sync Generator ............................................. 123
Frame Sync Mode Control Bits ................................. 123
I/O Pins ..................................................................... 121
Interrupts ................................................................... 128
Introduction ............................................................... 121
Master Frame Sync Operation .................................. 123
Operation .................................................................. 123
Operation During CPU Idle Mode ............................. 128
Operation During CPU Sleep Mode .......................... 128
Receive Slot Enable Bits........................................... 126
Receive Status Bits ................................................... 127
Register Map............................................................. 130
Sample Clock Edge Control Bit................................. 126
Slave Frame Sync Operation .................................... 124
Slot Enable Bits Operation with Frame Sync ............ 126
Slot Status Bits.......................................................... 128
cies (Table) ....................................................... 125
IDLE
) .................................................... 175
DD
)............................................. 174
PD
) ........................................ 176
Development Support ....................................................... 167
Device Configuration
Device Configuration Registers
Device Overview................................................................. 11
Disabling the UART .......................................................... 105
Divide Support .................................................................... 18
DSP Engine ........................................................................ 19
Dual Output Compare Match Mode .................................... 86
E
Electrical Characteristics .................................................. 171
Enabling and Setting Up UART
Enabling and Setting up UART
Enabling the UART ........................................................... 105
Equations
Errata .................................................................................... 9
Exception Sequence
External Clock Timing Requirements ............................... 182
External Interrupt Requests ................................................ 64
F
Fast Context Saving ........................................................... 64
Flash Program Memory ...................................................... 43
I
I/0 Ports
I/O Pin Specifications
I/O Ports.............................................................................. 53
I
2
C 10-Bit Slave Mode Operation ....................................... 93
Synchronous Data Transfers .................................... 126
Timing Requirements
Transmit Slot Enable Bits ......................................... 126
Transmit Status Bits.................................................. 127
Transmit/Receive Shift Register ............................... 121
Underflow Mode Control Bit...................................... 128
Word-Size Selection Bits .......................................... 123
Register Map ............................................................ 158
FBORPOR ................................................................ 156
FGS .......................................................................... 156
FOSC........................................................................ 156
FWDT ....................................................................... 156
Instructions (Table) ..................................................... 18
Multiplier ..................................................................... 21
Continuous Pulse Mode.............................................. 86
Single Pulse Mode...................................................... 86
AC............................................................................. 180
DC ............................................................................ 172
Alternate I/O ............................................................. 105
Setting up Data, Parity and Stop Bit Selections........ 105
ADC Conversion Clock ............................................. 133
Baud Rate................................................................. 107
Bit Clock Frequency.................................................. 125
COFSG Period.......................................................... 123
Serial Clock Rate ........................................................ 96
Time Quantum for Clock Generation ........................ 117
Trap Sources .............................................................. 62
Type A Timer ............................................................ 188
Type B Timer ............................................................ 189
Type C Timer ............................................................ 189
Register Map .............................................................. 55
Input.......................................................................... 178
Output ....................................................................... 178
Parallel (PIO) .............................................................. 53
Reception ................................................................... 94
AC-Link Mode................................................... 195
Multichannel, I
2
S Modes................................... 193
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