PIC16LF876-04/SO Microchip Technology, PIC16LF876-04/SO Datasheet - Page 86

• Manufacturer Part Number: PIC16LF876-04/SO
• Description: IC MCU FLASH 8KX14 EE A/D 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF876-04/SO

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC16LF
• No. Of I/o's: 24
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 4 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 22
• Interface Type: I2C/SPI/USART
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 3
• Processor Series: PIC16LF
• Core: PIC
• Data Ram Size: 368 B
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F87X
9.2.12
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high), and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag is set,
the SSPIF is set, and the baud rate generator is sus-
pended from counting, holding SCL low. The SSP is
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automati-
cally cleared. The user can then send an Acknowledge
bit at the end of reception, by setting the Acknowledge
Sequence Enable bit, ACKEN (SSPCON2<4>).
DS30292C-page 84
Note:
The SSP module must be in an IDLE state
before the RCEN bit is set, or the RCEN bit
will be disregarded.
I
2
C MASTER MODE RECEPTION
9.2.12.1
In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
9.2.12.2
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR, and the BF flag is already set
from a previous reception.
9.2.12.3
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
BF Status Flag
SSPOV Status Flag
WCOL Status Flag
2001 Microchip Technology Inc.