PIC24FJ128GA110-I/PT Microchip Technology, PIC24FJ128GA110-I/PT Datasheet - Page 235

• Manufacturer Part Number: PIC24FJ128GA110-I/PT
• Description: IC PIC MCU FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA110-I/PT

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCU
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

22.0
The triple comparator module provides three dual-input
comparators. The inputs to the comparator can be con-
figured to use any one of four external analog inputs, as
well as a voltage reference input from either the internal
band gap reference divided by two (V
comparator voltage reference generator.
FIGURE 22-1:
 2010 Microchip Technology Inc.
Note:
CCH<1:0>
CREF
C
C
C
V
C
CV
X
X
X
BG
X
TRIPLE COMPARATOR
MODULE
INB
INC
IND
INA
REF
/2
Section
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
(DS39710).
19.
Family
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
Select
Logic
Input
“Comparator
Reference
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
-
+
-
+
BG
-
+
/2) or the
Module”
Manual”,
C1
C2
C3
PIC24FJ256GA110 FAMILY
EVPOL<1:0>
EVPOL<1:0>
CPOL
EVPOL<1:0>
CPOL
CPOL
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module in shown in
Figure
comparator configurations are shown in
Each comparator has its own control register,
CMxCON
its operation. The output and event status of all three
comparators are provided in the CMSTAT register
(Register
Trigger/Interrupt
Trigger/Interrupt
Trigger/Interrupt
22-1. Diagrams of the possible individual
22-2).
(Register
Logic
Logic
Logic
22-1), for enabling and configuring
COE
COE
COE
CEVT
CEVT
COUT
CEVT
COUT
COUT
DS39905E-page 235
C1OUT
C2OUT
C3OUT
Figure
Pin
Pin
Pin
22-2.