DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 195

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401320IPT

TABLE 23-29: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS
FIGURE 23-14:
 2010 Microchip Technology Inc.
AC CHARACTERISTICS
CS60
CS61
CS62
CS65
CS66
CS70
CS71
CS72
CS75
CS76
CS80
Note 1:
Param
No.
Note: Refer to
(CKP = 0)
(CKP = 1)
SDIx
SCKx
SCKx
SDOx
2:
3:
T
T
T
T
T
T
T
T
T
T
T
Symbol
These parameters are characterized but not tested in manufacturing.
These values assume BIT_CLK frequency is 12.288 MHz.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
SACL
SYNCLO
SYNCHI
SYNC
OVDACL
RACL
BCLKL
BCLKH
BCLK
HACL
FACL
Figure 23-3
BIT_CLK Low Time
BIT_CLK High Time
BIT_CLK Period
Input Setup Time to
Falling Edge of BIT_CLK
Input Hold Time from
Falling Edge of BIT_CLK
SYNC Data Output Low Time
SYNC Data Output High Time
SYNC Data Output Period
Rise Time, SYNC, SDATA_OUT
Fall Time, SYNC, SDATA_OUT
Output Valid Delay from Rising
Edge of BIT_CLK
SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
Characteristic
SP35
SP31
SP11
for load conditions.
SP40 SP41
MSb In
MSb
SP10
(1,2)
Bit 14 - - - -1
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature
Min
Bit 14 - - - - - -1
36
36
—
—
—
—
—
—
—
—
—
Typ
40.7
40.7
81.4
19.5
20.8
1.3
dsPIC30F3014/4013
10
10
—
—
—
SP21
SP20
(3)
SP30
Max
45
45
10
10
25
25
15
—
—
—
—
SP20
SP21
LSb In
LSb
-40°C  T
-40°C  T
Units
ns
ns
ns
ns
ns
s
s
s
ns
ns
ns
A
A
Bit clock is input
Note 1
Note 1
Note 1
C
C
 +85°C for Industrial
 +125°C for Extended
LOAD
LOAD
Conditions
= 50 pF, V
= 50 pF, V
DS70138G-page 195
DD
DD
= 5V
= 5V