ATMEGA16L-8PU Atmel, ATMEGA16L-8PU Datasheet - Page 166
ATMEGA16L-8PU
Manufacturer Part Number
ATMEGA16L-8PU
Description
IC AVR MCU 16K 8MHZ 3V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA16L-8MI.pdf
(26 pages)
2.ATMEGA16L-8MI.pdf
(357 pages)
3.ATMEGA16-16PU.pdf
(358 pages)
Specifications of ATMEGA16L-8PU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
512 Bytes
Input Output
32
Interface
JTAG/SPI/UART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.7-5.5 V
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 166 of 357
- Download datasheet (8Mb)
USART Control and
Status Register C –
UCSRC
2466T–AVR–07/10
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDR.
The UCSRC Register shares the same I/O location as the UBRRH Register. See the
UBRRH/ UCSRC Registers” on page 162
• Bit 7 – URSEL: Register Select
This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when
reading UCSRC. The URSEL must be one when writing the UCSRC.
• Bit 6 – UMSEL: USART Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
Table 63. UMSEL Bit Settings
• Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.
If a mismatch is detected, the PE Flag in UCSRA will be set.
Table 64. UPM Bits Settings
• Bit 3 – USBS: Stop Bit Select
This bit selects the number of Stop Bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 65. USBS Bit Settings
Bit
Read/Write
Initial Value
UPM1
UMSEL
0
0
1
1
0
1
URSEL
USBS
R/W
7
1
0
1
UMSEL
R/W
6
0
UPM0
Mode
Asynchronous Operation
Synchronous Operation
0
1
0
1
UPM1
R/W
5
0
UPM0
R/W
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
4
0
section which describes how to access this register.
USBS
R/W
3
0
UCSZ1
Stop Bit(s)
R/W
2
1
1-bit
2-bit
UCSZ0
R/W
1
1
ATmega16(L)
UCPOL
R/W
0
0
UCSRC
“Accessing
166
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