ATMEGA16L-8PU Atmel, ATMEGA16L-8PU Datasheet - Page 147

• Manufacturer Part Number: ATMEGA16L-8PU
• Description: IC AVR MCU 16K 8MHZ 3V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 32
• Interface: JTAG/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 16K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.7-5.5 V
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Double Speed
Operation (U2X)
External Clock
2466T–AVR–07/10
Table 60. Equations for Calculating Baud Rate Register Setting
Note:
Some examples of UBRR values for some system clock frequencies are found in
page
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect
for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External clocking is used by the synchronous Slave modes of operation. The description in this
section refers to
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and receiver. This process introduces
a two CPU clock period delay and therefore the maximum external XCK clock frequency is lim-
ited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
Operating Mode
Asynchronous Normal Mode
(U2X = 0)
Asynchronous Double Speed Mode
(U2X = 1)
Synchronous Master Mode
BAUD Baud rate (in bits per second, bps)
f
UBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)
OSC
168).
1. The baud rate is defined to be the transfer rate in bit per second (bps).
System Oscillator clock frequency
osc
depends on the stability of the system clock source. It is therefore recommended to
Figure 70
for details.
BAUD
BAUD
BAUD
Equation for Calculating
f
XCK
Baud Rate
=
=
=
<
-------------------------------------- -
16 UBRR
---------------------------------- -
8 UBRR
---------------------------------- -
2 UBRR
f
---------- -
(
(
OSC
(
4
f
f
f
OSC
OSC
OSC
(1)
+
+
+
1
1
1
)
)
)
UBRR
UBRR
UBRR
Calculating UBRR
Equation for
ATmega16(L)
=
=
=
Value
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
OSC
OSC
OSC
Table 68
–
–
–
(see
147