PIC24FJ128GA010-I/PF Microchip Technology, PIC24FJ128GA010-I/PF Datasheet - Page 130

• Manufacturer Part Number: PIC24FJ128GA010-I/PF
• Description: IC PIC MCU FLASH 64KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA010-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (43K x 24)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 84
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Controller Family/series: PIC24
• No. Of I/o's: 84
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ128GA FAMILY
REGISTER 15-2:
DS39747A-page 128
bit 15
bit 14
bit 13-11 Unimplemented: Read as ‘0’
bit 10
bit 9
bit 8
bit 7
bit 6
.
Upper Byte:
bit 15
ACKSTAT
R-0 HSC
ACKSTAT: Acknowledge Status bit
(When operating as I
1 = NACK received from slave
0 = ACK received from slave
Hardware set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit
(When operating as I
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission.
Hardware clear at end of slave Acknowledge.
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address.
Hardware clear at Stop detection.
ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address.
Hardware clear at Stop detection.
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CRSR to I2CxRCV (cleared by software).
Legend:
R = Readable bit
-n = Value at POR
R-0 HSC
TRSTAT
Lower Byte:
bit 7
R/C-0 HS
IWCOL
I2CxSTAT: I2Cx STATUS REGISTER
U-0
—
2
2
R/C-0 HS
C master. Applicable to master transmit operation.)
C master. Applicable to master transmit operation.)
I2COV
C = Clearable bit
‘1’ = Bit is set
U-0
—
Advance Information
R-0 HSC
D/A
U-0
—
R/C-0 HSC R/C-0 HSC
U = Unimplemented bit, read as ‘0’
HS = Set in Hardware
‘0’ = Bit is cleared
P
R/C-0 HS
BCL
S
2
R-0 HSC
GCSTAT
C module is busy
R-0 HSC
HSC = Hardware Set/Cleared
x = Bit is unknown
R/W
© 2005 Microchip Technology Inc.
R-0 HSC
ADD10
R-0 HSC
bit 8
RBF
R-0 HSC
TBF
bit 0