PIC24FJ128GA010-I/PF Microchip Technology, PIC24FJ128GA010-I/PF Datasheet
PIC24FJ128GA010-I/PF
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PIC24FJ128GA010-I/PF Summary of contents
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... PIC24FJ128GA010 Family Silicon Errata and Data Sheet Clarification The PIC24FJ128GA010 Family devices that you have received conform functionally to the current Device Data Sheet (DS39747D), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1 ...
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... PIC24FJ128GA010 FAMILY TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number Core — C™ — 2. UART — 3. Resets — 4. Timers — 5. SPI Enhanced 6. mode JTAG Programming 7. A/D — — 9. UART — 10. SPI Master mode 11. CPU — 12. PMP — 13 PMP Master mode 14. ...
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... C Slave mode 55. Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Issue Summary Module in Slave mode may ignore SS pin and receive data anyway. Two-Speed Start-up failure when IESO is enabled. Unimplemented CLKDIV bits reset to ‘1’. ...
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... PIC24FJ128GA010 FAMILY TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Item Module Feature Number — 56. SPI Master mode 57. RTCC Alarm 58. I/O Pins — 59. SPI Framed 60. modes SPI Enhanced 61. mode Core Code 62. Protection Note 1: Only those issues indicated in the last column apply to the current silicon revision. ...
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... © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 3. Module: UART With the parity option enabled, a parity error, indicated with the PERR bit (UxSTA<3>) being set, may occur if the Baud Rate Generator contains an odd value. This affects both even and odd parity options. ...
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... PIC24FJ128GA010 FAMILY 5. Module: Timers With Timer2 and Timer3 configured in 32-bit mode by setting T2CON<3>, a Special Event Trigger to start an A/D conversion may not occur when the most significant word of the Period register, PR3, is ‘0’. Work around Either write PR3 to a non-zero value or configure ...
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... © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 12. Module: CPU A DISI instruction may be ignored if the command is executed in the same instruction cycle as when the DISICNT register decrements to zero. For example DISI #5 instruction is performed, the DISICNT will decrement to zero in six instruction cycles (5 instruction cycles for the DISI command plus 1 for the instruction execution) ...
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... PIC24FJ128GA010 FAMILY 14. Module: PMP (Master Mode) With the PMP in Master mode (MODE<1:0> 10) with the increment/decrement feature enabled (INCM<1:0> 10), the address may not automatically change when the PMDINx register is read. This issue may occur when multiple back-to-back reads are performed. Work around ...
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... © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 22. Module: UART When UTXISEL<1:0> = 10, a UART interrupt flag should be set after one byte from the FIFO is transferred to the Transmit Shift Register (TSR). Instead, the interrupt flag may be set only after all bytes are transferred from the FIFO and the FIFO is empty. This behavior is similar to the UTXISEL< ...
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... PIC24FJ128GA010 FAMILY 25. Module: UART (Auto-Baud) With the auto-baud feature selected, the Sync Break character (0x55) may be loaded into the FIFO as data. Work around To prevent the Sync Break character from being loaded into the FIFO, load the UxBRG register with either 0x0000 or 0xFFFF prior to enabling the auto-baud feature (ABAUD = 1) ...
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... © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 33. Module: Core (Traps clock failure occurs when the device is in Idle mode, the oscillator failure trap does not vector to the Trap Service Routine. Instead, the device will simply wake-up from Idle mode and continue code execution if the Fail-Safe Clock Monitor (FSCM) is enabled ...
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... PIC24FJ128GA010 FAMILY 2 36. Module (Slave Mode) 2 During I C Slave mode transactions, Data/Address bit, D/A, may not update during the data frame. This affects both 7 and 10-Bit Addressing modes slave receptions are not affected by this issue. Work around Use the Read/Write bit, R/W, and the Transmit Buffer Full Status Bit, TBF, to determine whether address or data information is being received ...
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... Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 2 45. Module After the ACKSTAT bit is set, while receiving a NACK from the master or a slave, it may be cleared by the reception of a Start or Stop bit. Work around Store the value of the ACKSTAT bit immediately after receiving a NACK ...
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... PIC24FJ128GA010 FAMILY 47. Module: Core (Instruction Set instruction producing a read-after-write stall condition is executed inside a REPEAT loop, the instruction will be executed fewer times than was intended. For example, this loop: repeat #0xf inc [w1],[++w1] will execute less than 15 times. Work around Avoid using REPEAT to repetitively execute instructions that create a stall condition ...
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... © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 2 54. Module (Master Mode) Under certain circumstances, a module operating in Master mode may Acknowledge its own com- mand addressed to a slave device. This happens when the following occurs: • 10-Bit Addressing mode is used (A10M = 1); ...
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... PIC24FJ128GA010 FAMILY 2 56. Module The Transmit Buffer Full (TBF) flag (I2CxSTAT<0>) may not be cleared by hardware if a collision on the bus occurs before the first falling clock edge during a transmission. Work around None. Affected Silicon Revisions EXAMPLE 1: CHECKING THE STATE OF SPIxIF AGAINST THE SPI CLOCK while(IFS0bits ...
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... All I/O Pins Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 59. Module: I/O Pins The I/O pin output, V Table 3 below. Work around None ...
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... PIC24FJ128GA010 FAMILY 60. Module: SPI (Framed SPI Modes) Framed SPI modes, as described in the device data sheet, are not supported. When using the module, verify the FRMEN bit (SPIxCON2<15>) is cleared. All other SPI modes function as described. Work around None. Affected Silicon Revisions A2 A3 ...
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... The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39747D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. None. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS80471A-page 19 ...
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... This document replaces these errata documents: • “PIC24FJ128GA010 Family Rev. A2 Silicon Errata” (DS80275) • “PIC24FJ128GA010 Family Rev. A3 Silicon Errata” (DS80295) • “PIC24FJ128GA010 Family Rev. A4 Silicon Errata” (DS80330) • “PIC24FJ128GA010 Family Rev. C1 Silicon Errata” (DS80422) © 2009 Microchip Technology Inc has been ...
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... PICDEM, PICDEM.net, PICtail, PIC Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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