AT91SAM7S321-MU Atmel, AT91SAM7S321-MU Datasheet - Page 208

• Manufacturer Part Number: AT91SAM7S321-MU
• Description: MCU ARM 32K HI SPD FLASH 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S321-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, I2S, SPI, SSC, TWI, UART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 10 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.9.9
Register Name:
Access Type:
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
• DIV: Divider
• PLLCOUNT: PLL Counter
Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• OUT: PLL Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1.
• USBDIV: Divider for USB Clock (Does not Pertain to AT91SAM73S2/16
208
DIV
0
1
2 - 255
31
23
15
–
7
0
0
1
1
AT91SAM7S Series Preliminary
PMC Clock Generator PLL Register
OUT
USBDIV
30
22
14
CKGR_PLLR
Read-write
–
6
0
1
0
1
29
21
13
5
USBDIV
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIV.
Divider for USB Clock(s)
Divider output is PLL clock output.
Divider output is PLL clock output divided by 2.
Divider output is PLL clock output divided by 4.
Reserved.
28
20
12
4
MUL
DIV
27
19
11
3
–
PLLCOUNT
26
18
10
2
MUL
25
17
9
1
6175K–ATARM–30-Aug-10
24
16
8
0