PIC24HJ128GP506-I/PT Microchip Technology, PIC24HJ128GP506-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC24HJ128GP506-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ128GP506-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (43K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 13
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 18-ch x 12-bit
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1. Module: SPI with 1:1 Prescaler
2. Module: SPI Master Reception for Bit
3. Module: ADC with Sample/Hold CH3
© 2006 Microchip Technology Inc.
The SPI1 and SPI2 modules do not generate any
serial clock signals and, therefore, do not function
correctly
PPRE<1:0>
SPRE<2:0> (SPIxCON1<4:2>) bits:
• PPRE = 11, SPRE = 111
Work around
Users may set up the SPI module with any
prescale ratio other than 1:1.
Master mode receptions using the SPI1 and SPI2
module do not function correctly for bit rates above
8 Mbps if the Master has the SMP bit
(SPIxCON1<9>) cleared (Master samples data at
the middle of the serial clock period).
In this case, the data transmitted by the Slave is
received shifted right by one bit by the Master. For
example, if the data transmitted by the Slave was
0xAAAA, the data received by the Master would be
0x5555 (0xAAAA shifted right by one bit).
Work around
Users may set up the SPI module so that the bit
rate is 8 Mbps or lower.
Alternatively, the bit rate can be configured higher
than 8 Mbps, but the SMP bit (SPIxCON1<9>) of
the SPI Master must be set (Master samples data
at the end of the serial clock period).
The Sample/Hold amplifier CH3 does not function
correctly when used with the Analog-to-Digital
Converter (ADC) modules. The corresponding
conversion result is always read as 0x0000.
Work around
Do not use the Sample/Hold amplifier CH3 with the
ADC1 or ADC2 module. You may use CH0, CH1
and CH2.
Rates above 8 Mbps
for
(SPIxCON1<1:0>)
the
following
PIC24H ENGINEERING SAMPLES
values
and
of
the
the
4. Module: LATC and LATD Reads
5. Module: DMA Single-Shot Mode
6. Module: Watchdog Timer
The LATC and LATD register reads do not func-
tion. Performing a read or read-modify-write oper-
ation on the LATC register or the LATD register will
not function.
Do not perform read or read-modify-write opera-
tions on the LATC and LATD registers. Inspect the
disassembly listing of any user application soft-
ware that may be accessing the LATC or LATD
register, to ensure that read or read-modify-write
operations are not being performed on these
registers.
To verify the contents of the LATC register, perform
the following steps:
• Write to LATC
• Make a PORTC pin an output
• Read the PORTC register
The same steps can be performed to verify the
contents of the LATD register.
Note: The Port pin state, and therefore the read
The DMA Single-Shot mode does not function cor-
rectly for more than one block transfer. After one
block transfer, the DMA channel becomes
unusable until a device reset occurs.
Work around
If more than one DMA data block transfers are
required during the entire program execution, the
user application may set up the required DMA
channel to operate in Continuous mode, and dis-
able the DMA channel every time the
corresponding DMA interrupt has occurred.
However, if only one DMA data block transfer is
required for a particular DMA channel during the
entire program execution, the Single-Shot mode
may be used.
When the WDT is disabled and the WDT Window
is enabled, a WDT time out will occur. This will
cause the device to reset unexpectedly. The WDT
is
(FWDT<7>). The WDT Window feature is enabled
by clearing the WINDIS bit (FWDT<6>).
Work around
In order to prevent an unexpected WDT time out
when the WDT is disabled, disable the WDT
Window feature by setting the WINDIS bit
(FWDT<6>).
disabled by clearing the
value, depends on the load attached to the
Port pin.
DS80260B-page 3
FWDTEN
bit