ATMEGA16-16MU Atmel, ATMEGA16-16MU Datasheet - Page 286

IC AVR MCU 16K 16MHZ 5V 44-QFN

ATMEGA16-16MU

Manufacturer Part Number
ATMEGA16-16MU
Description
IC AVR MCU 16K 16MHZ 5V 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16-16MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
JTAG/SPI/UART
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
MLF
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Package
44MLF
Family Name
ATmega
Maximum Speed
16 MHz
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Virtual Flash Page
Load Register
2466T–AVR–07/10
Figure 142. State Machine Sequence for Changing/Reading the Data Word
The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of
bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically trans-
ferred to the Flash page buffer byte by byte. Shift in all instruction words in the page, starting
with the LSB of the first instruction in the page and ending with the MSB of the last instruction in
the page. This provides an efficient way to load the entire Flash page buffer before executing
Page Write.
1
0
Test-Logic-Reset
Run-Test/Idle
0
1
1
0
Select-DR Scan
Capture-DR
Update-DR
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
1
0
0
1
0
1
1
0
1
1
0
0
1
0
Select-IR Scan
Capture-IR
ATmega16(L)
Update-IR
Pause-IR
Exit1-IR
Exit2-IR
Shift-IR
1
0
0
1
0
1
1
0
1
1
0
0
286

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