DSPIC33FJ128GP306A-I/PT Microchip Technology, DSPIC33FJ128GP306A-I/PT Datasheet - Page 189

• Manufacturer Part Number: DSPIC33FJ128GP306A-I/PT
• Description: IC DSPIC MCU/DSP 128K 64-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP306A-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: No
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: I2C/SPI/UART
• On-chip Adc: 18-chx10-bit|18-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and
Multi-Master modes of the I
standard, with a 16-bit interface.
The
have up to two I
and I2C2. Each I
SCLx pin is clock and the SDAx pin is data.
Each I
features:
• I
• I
• I
• I
• Serial clock synchronization for I
• I
© 2011 Microchip Technology Inc.
operation
addressing
addressing
master and slaves
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
collision and will arbitrate accordingly
2
2
2
2
2
Note 1: This data sheet summarizes the features
C interface supporting both master and slave
C Slave mode supports 7-bit and 10-bit
C Master mode supports 7-bit and 10-bit
C Port allows bidirectional transfers between
C supports multi-master operation; detects bus
2
dsPIC33FJXXXGPX06A/X08A/X10A
C module ‘x’ (x = 1 or 2) offers the following key
2: Some registers and associated bits
INTER-INTEGRATED
CIRCUIT™ (I
of the dsPIC33FJXXXGPX06A/X08A/
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the infor-
mation in this data sheet, refer to Section
19. “Inter-Integrated Circuit™ (I
(DS70195) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
2
C interface modules, denoted as I2C1
2
C module has a 2-pin interface: the
dsPIC33FJXXXGPX06A/X08A/X10A
2
C™)
2
C serial communication
2
C) module provides
2
C port can be
2
devices
C™)”
in
17.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, please refer to the “dsPIC33F/PIC24H
Family Reference Manual”.
17.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
I2CxRSR is the shift register used for shifting data,
whereas I2CxRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CxRCV is the receive buffer. I2CxTRN is the transmit
register to which bytes are written during a transmit
operation.
The I2CxADD register holds the slave address. A
status bit, ADD10, indicates 10-bit Address mode. The
I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
2
2
2
C slave operation with 7-bit addressing
C slave operation with 10-bit addressing
C master operation with 7-bit or 10-bit addressing
2
C module can operate either as a slave or a
Operating Modes
I
2
C Registers
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
DS70593C-page 189