PIC16F84-10/SO Microchip Technology, PIC16F84-10/SO Datasheet - Page 223
![IC MCU FLASH 1KX14 EE 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F84-10/SO
Manufacturer Part Number
PIC16F84-10/SO
Description
IC MCU FLASH 1KX14 EE 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16LF84A-04P.pdf
(125 pages)
3.PIC16LF84A-04P.pdf
(4 pages)
Specifications of PIC16F84-10/SO
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16F
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
10MHz
No. Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MIL309-1075 - ADAPTER 18-SOIC TO 18-SOIC309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F84-10/SO
Manufacturer:
AD
Quantity:
34
Part Number:
PIC16F84-10/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 223 of 688
- Download datasheet (3Mb)
15.2
1997 Microchip Technology Inc.
Control Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Register 15-1: SSPSTAT: Synchronous Serial Port Status Register
bit 7
SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
CKE: SPI Clock Edge Select
CKP = 0 (SSPCON<4>)
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1 (SSPCON<4>)
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
(I
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit
(I
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next start bit, stop bit, or not ACK bit.
1 = Read
0 = Write
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
2
2
R/W-0
C mode only. This bit is cleared when the SSP module is disabled)
C mode only. This bit is cleared when the SSP module is disabled)
SMP
2
C mode only)
R/W-0
CKE
2
C modes)
2
C mode only)
W = Writable bit
R-0
D/A
2
(Figure
C mode only)
2
C mode only)
15-3,
R-0
P
Figure
15-4, and
- n = Value at POR reset
Section 15. SSP
R-0
S
Figure
R/W
R-0
15-5)
DS31015A-page 15-3
R-0
UA
bit 0
R-0
BF
15
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