PIC16C773-I/SO Microchip Technology, PIC16C773-I/SO Datasheet - Page 107

• Manufacturer Part Number: PIC16C773-I/SO
• Description: IC MCU OTP 4KX14 A/D PWM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C773-I/SO

• Program Memory Type: OTP
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/SSP/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: PIC16C773-04I/SO

9.3
In Synchronous Master mode, the data is transmitted in
a half-duplex manner i.e. transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition enable bit SPEN (RCSTA<7>) is set in order to
configure the RC6/TX/CK and RC7/RX/DT I/O pins to
CK (clock) and DT (data) lines respectively. The Master
mode indicates that the processor transmits the master
clock on the CK line. The Master mode is entered by
setting bit CSRC (TXSTA<7>).
9.3.1
The USART transmitter block diagram is shown in
Figure
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit, TXIF (PIR1<4>) is set. The interrupt can be
TABLE 9-8
Address Name
0Ch
18h
19h
8Ch
98h
99h
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
1999 Microchip Technology Inc.
9-3. The heart of the transmitter is the transmit
USART Synchronous Master Mode
USART SYNCHRONOUS MASTER
TRANSMISSION
TXREG USART Transmit Register
SPBRG Baud Rate Generator Register
PIR1
RCSTA
PIE1
TXSTA
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
PSPIF
PSPIE
SPEN
CSRC
Bit 7
(1)
(1)
ADIF
ADIE
Bit 6
RX9
TX9
SREN CREN ADDEN
TXEN SYNC
RCIF
RCIE
Bit 5
Bit 4
TXIF
TXIE
Advance Information
SSPIE
SSPIF
Bit 3
—
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
BRGH
FERR
Bit 2
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory so it is not
available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
OERR
TRMT
Bit 1
(Section
RX9D
TX9D
Bit 0
9.1).
PIC16C77X
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
Value on:
POR,
BOR
DS30275A-page 107
other Resets
Value on all
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000