PIC24HJ128GP206-I/PT Microchip Technology, PIC24HJ128GP206-I/PT Datasheet - Page 9
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PIC24HJ128GP206-I/PT
Manufacturer Part Number
PIC24HJ128GP206-I/PT
Description
IC PIC MCU FLASH 64KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
6.PIC24HJ128GP206-IPT.pdf
(286 pages)
7.PIC24HJ128GP306-IPT.pdf
(288 pages)
Specifications of PIC24HJ128GP206-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (43K x 24)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
13
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
18-ch x 12-bit
Controller Family/series
PIC24
No. Of I/o's
53
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ128GP206-I/PT
Manufacturer:
SMSC
Quantity:
7 600
Company:
Part Number:
PIC24HJ128GP206-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24HJ128GP206-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.2
Before programming, the programmer must confirm
that the programming executive is stored in executive
memory. The procedure for this task is illustrated in
Figure
First, ICSP mode is entered. Then, the unique
Application ID Word stored in executive memory is read.
If the programming executive is resident, the correct
Application ID Word is read and programming can
resume as normal. However, if the Application ID Word is
not present, the programming executive must be
programmed to executive code memory using the
method described in
Programming Executive to
for the Application ID of each device.
Section 5.0 “Device Programming – ICSP”
the ICSP programming method.
the Application ID Word”
reading the Application ID Word in ICSP mode.
FIGURE 3-2:
© 2010 Microchip Technology Inc.
Note 1: See
3-2.
Enter ICSP™ Mode
by reading Address
Enter Enhanced
Exit ICSP Mode
Confirming the Presence of the
Programming Executive
Application ID
Application ID
Sanity Check
ICSP Mode
present?
Check the
0x8007F0
Start
End
sion”
device.
Is
Yes
TABLE 7-1: “Device IDs and Revi-
(1)
for the Application ID of each
Section 6.0 “Programming the
CONFIRMING PRESENCE
OF PROGRAMMING
EXECUTIVE
describes the procedure for
No
Prog. Executive must
Memory”. See
Section 5.11 “Reading
be Programmed
describes
Table 7-1
3.3
As illustrated in
Program/Verify mode requires three steps:
1.
2.
3.
The programming voltage applied to MCLR is V
which is essentially V
devices. There is no minimum time requirement for
holding at V
least P18 must elapse before presenting the key
sequence on PGDx.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more
hexadecimal format). The device will enter Program/
Verify mode only if the key sequence is valid. The Most
Significant bit (MSb) of the most significant nibble must
be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval
time of at least P19 and P7 must elapse before
presenting data on PGDx. Signals appearing on PGDx
before P7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
Note:
The MCLR pin is briefly driven high then low.
A 32-bit key sequence is clocked into PGDx.
MCLR is then driven high within a specified
period of time and held.
easily
Entering Enhanced ICSP Mode
When programming a device without
Peripheral Pin Select (PPS) and in
Enhanced ICSP mode, the SPI output pin
(SDOx) may toggle while the device is
being programmed.
IH
. After V
Figure
remembered
DD
IH
3-3, entering Enhanced ICSP
in case of dsPIC33F/PIC24H
is removed, an interval of at
as
0x4D434850
DS70152H-page 9
IH
must be
IH
in
,