PIC24HJ128GP206-I/PT Microchip Technology, PIC24HJ128GP206-I/PT Datasheet
![IC PIC MCU FLASH 64KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24HJ128GP206-I/PT
Specifications of PIC24HJ128GP206-I/PT
Available stocks
Related parts for PIC24HJ128GP206-I/PT
PIC24HJ128GP206-I/PT Summary of contents
Page 1
... PIC24HJXXXGPX06/X08/X10 © 2009 Microchip Technology Inc. Data Sheet High-Performance, 16-Bit Microcontrollers DS70175H ...
Page 2
... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... Output pins can drive from 3.0V to 3.6V • All digital input pins are 5V tolerant • sink on all I/O pins © 2009 Microchip Technology Inc. On-Chip Flash and SRAM: • Flash program memory 256 Kbytes • Data SRAM Kbytes (includes 2 Kbytes ...
Page 4
... Fully static design • 3.3V (±10%) operating voltage • Industrial temperature • Low-power consumption Packaging: • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) • 64-pin TQFP (10x10x1 mm) Note: See the device variant tables for exact peripheral features per device. © 2009 Microchip Technology Inc. ...
Page 5
... PIC24H Family Controllers Program Device Pins Flash Memory (KB) PIC24HJ64GP206 64 64 PIC24HJ64GP210 100 64 PIC24HJ64GP506 64 64 PIC24HJ64GP510 100 64 PIC24HJ128GP206 64 128 PIC24HJ128GP210 100 128 PIC24HJ128GP506 64 128 PIC24HJ128GP510 100 128 PIC24HJ128GP306 64 128 PIC24HJ128GP310 100 128 PIC24HJ256GP206 64 ...
Page 6
... REF Note: The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins. DS70175H-page 4 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/U1CTS/INT2/RD9 42 IC1/INT1/RD8 PIC24HJ64GP206 OSC2/CLKO/RC15 PIC24HJ128GP206 39 OSC1/CLKIN/RC12 PIC24HJ256GP206 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 = Pins are tolerant SS DD © 2009 Microchip Technology Inc. ...
Page 7
... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 PIC24HJ128GP306 Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 ...
Page 8
... SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF DS70175H-page 6 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/U1CTS/INT2/RD9 42 IC1/INT1/RD8 41 V PIC24HJ64GP506 40 OSC2/CLKO/RC15 PIC24HJ128GP506 39 OSC1/CLKIN/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 = Pins are tolerant SS DD © 2009 Microchip Technology Inc. ...
Page 9
... SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 PGED3/AN0/CN2/RB0 25 © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 PIC24HJ64GP210 PIC24HJ128GP210 PIC24HJ128GP310 PIC24HJ256GP210 = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 73 72 OC1/RD0 IC4/RD11 71 70 IC3/RD10 IC2/RD9 69 IC1/RD8 68 INT4/RA15 67 INT3/RA14 OSC2/CLKO/RC15 64 63 OSC1/CLKIN/RC12 ...
Page 10
... PGEC3/AN1/CN3/RB1 24 PGED3/AN0/CN2/RB0 25 DS70175H-page 8 PIC24HJ64GP510 PIC24HJ128GP510 = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 OC1/RD0 72 71 IC4/RD11 70 IC3/RD10 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 64 63 OSC1/CLKIN/RC12 TDO/RA5 61 TDI/RA4 60 SDA2/RA3 59 58 SCL2/RA2 SCL1/RG2 57 SDA1/RG3 56 55 SCK1/INT0/RF6 54 SDI1/RF7 SDO1/RF8 53 52 U1RX/RF2 51 U1TX/RF3 © 2009 Microchip Technology Inc. ...
Page 11
... AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 PGED3/AN0/CN2/RB0 25 © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 PIC24HJ256GP610 = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 OC1/RD0 72 71 IC4/RD11 70 IC3/RD10 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 ...
Page 12
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70175H-page 10 © 2009 Microchip Technology Inc. ...
Page 13
... Manual”, which is available from the Microchip web site (www.microchip.com). This document contains device specific information for the following devices: • PIC24HJ64GP206 • PIC24HJ64GP210 • PIC24HJ64GP506 • PIC24HJ64GP510 • PIC24HJ128GP206 • PIC24HJ128GP210 • PIC24HJ128GP506 • PIC24HJ128GP510 • PIC24HJ128GP306 • PIC24HJ128GP310 • PIC24HJ256GP206 • PIC24HJ256GP210 • ...
Page 14
... Latch Control Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support 16-bit ALU MCLR ECAN1,2 UART1,2 CN1-23 SPI1,2 I2C1,2 PORTA DMA RAM PORTB DMA 16 Controller PORTC PORTD 16 PORTE 16 16 PORTF 16 PORTG © 2009 Microchip Technology Inc. ...
Page 15
... ST RG12-RG15 I/O ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Description Analog input channels. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. External clock source input. Always associated with OSC1 pin function. ...
Page 16
... Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input O = Output P = Power I = Input © 2009 Microchip Technology Inc. ...
Page 17
... REF reference for ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...
Page 18
... MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V IH for and V ) and fast signal shown in Figure 2- EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR PIC24H JP C and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. ...
Page 19
... REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 2.6 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “ ...
Page 20
... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor to V unused pins and drive the output to logic low. DS70175H-page © 2009 Microchip Technology Inc. ...
Page 21
... A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model PIC24HJXXXGPX06/X08/X10 is shown in Figure 3-2. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 3.1 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). ...
Page 22
... DS70175H-page 20 X Data Bus Data Latch PCH PCL X RAM Address Loop Control Latch Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2009 Microchip Technology Inc. ...
Page 23
... FIGURE 3-2: PIC24HJXXXGPX06/X08/X10 PROGRAMMER’S MODEL PC22 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH 3.3 CPU Control Registers © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer ...
Page 24
... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70175H-page 22 U-0 U-0 — — (2) R-0 R/W-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W bit 0 © 2009 Microchip Technology Inc. ...
Page 25
... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — ...
Page 26
... The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. © 2009 Microchip Technology Inc. ...
Page 27
... Flash Memory (22K instructions) Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 4.1 Program Address Space The program address PIC24HJXXXGPX06/X08/X10 devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remap- ping as described in Section 4.4 “ ...
Page 28
... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vec- tor tables is provided in Section 7.1 “Interrupt Vector Table”. least significant word Instruction Width PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2009 Microchip Technology Inc. ...
Page 29
... Data byte writes only write to the corresponding side of the array or register which matches the byte address. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or translating from 8-bit MCU code ...
Page 30
... Optionally Mapped into Program Memory 0xFFFF DS70175H-page 28 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x2000 DMA RAM 0x27FE 0x2800 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2009 Microchip Technology Inc. ...
Page 31
... Memory locations in the DMA RAM space are accessible simultaneously by the CPU and the DMA controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 LSB Address 16 bits ...
Page 32
TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
Page 33
TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX10 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — — — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE ...
Page 34
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF ...
Page 35
TABLE 4-6: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
Page 36
TABLE 4-7: INPUT CAPTURE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ...
Page 37
TABLE 4-8: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...
Page 38
TABLE 4-9: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — I2C1TRN 0202 — — — I2C1BRG 0204 — — — I2C1CON 0206 I2CEN — I2CSIDL SCLREL I2C1STAT 0208 ...
Page 39
TABLE 4-12: UART2 REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr U2MODE 0230 UARTEN — USIDL IREN U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — U2TXREG 0234 — — — — U2RXREG 0236 — — — ...
Page 40
TABLE 4-15: ADC1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...
Page 41
TABLE 4-17: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...
Page 42
TABLE 4-17: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5PAD 03C4 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB ...
Page 43
TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = FOR PIC24HJXXXGP506/510/610 DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — — C1VEC 0404 ...
Page 44
TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR PIC24HJXXXGP506/510/610 DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 ...
Page 45
TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR PIC24HJXXXGP506/510/610 DEVICES ONLY (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11EID 046E EID<15:8> C1RXF12SID 0470 SID<10:3> C1RXF12EID 0472 EID<15:8> C1RXF13SID 0474 SID<10:3> C1RXF13EID 0476 EID<15:8> ...
Page 46
TABLE 4-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = FOR PIC24HJ256GP610 DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 C2CTRL1 0500 — — CSIDL C2CTRL2 0502 — — — C2VEC 0504 — — — C2FCTRL ...
Page 47
TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR PIC24HJ256GP610 DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0500- 051E C2BUFPNT1 0520 F3BP<3:0> C2BUFPNT2 0522 F7BP<3:0> C2BUFPNT3 0524 F12BP<3:0> C2BUFPNT4 0526 F15BP<3:0> C2RXM0SID 0530 ...
Page 48
TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR PIC24HJ256GP610 DEVICES ONLY (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C2RXF11EID 056E C2RXF12SID 0570 C2RXF12EID 0572 C2RXF13SID 0574 C2RXF13EID 0576 C2RXF14SID 0578 C2RXF14EID 057A C2RXF15SID ...
Page 49
TABLE 4-24: PORTA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 TRISA15 TRISA14 TRISA13 TRISA12 PORTA 02C2 RA15 RA14 RA13 RA12 LATA 02C4 LATA15 LATA14 LATA13 LATA12 ODCA 06C0 ODCA15 ODCA14 — ...
Page 50
TABLE 4-28: PORTE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISE 02D8 — — — — PORTE 02DA — — — — LATE 02DC — — — — Legend unknown value ...
Page 51
TABLE 4-31: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...
Page 52
... Register Indirect • Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. © 2009 Microchip Technology Inc. modes are ...
Page 53
... DISI instruction uses a 14-bit unsigned literal field. In some instructions, the source of an oper- and or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Description The address of the file register is specified explicitly. ...
Page 54
... PC<22:1> 0 0xxx xxxx xxxx xxxx TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx xxx xxxx xxxx xxxx © 2009 Microchip Technology Inc. <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> ...
Page 55
... Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Program Counter 0 ...
Page 56
... TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in 0x800000 the user memory area © 2009 Microchip Technology Inc. ...
Page 57
... PSV- PAG is mapped into the upper half of the data memory space... © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
Page 58
... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175H-page 56 © 2009 Microchip Technology Inc. ...
Page 59
... Program Counter Using 1/0 Table Instruction User/Configuration Space Select © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 signal controller just before shipping the product. This also allows the most recent firmware or a custom firm- ware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions ...
Page 60
... NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. stalls (waits) until the PROGRAMMING TIME T )% × FRC Accuracy FRC Tuning 11064 Cycles = × × 0.02 1 0.00375 – 11064 Cycles = × × 0.02 – 1 0.00375 – © 2009 Microchip Technology Inc. ...
Page 61
... Memory page erase operation (ERASE = operation (ERASE = 0) 0001 = Memory row program operation (ERASE = operation (ERASE = 1) 0000 = Program or erase a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 (1) U-0 U-0 — ...
Page 62
... Initialize in-page EA<15:0> pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2009 Microchip Technology Inc. ...
Page 63
... MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ...
Page 64
... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175H-page 62 © 2009 Microchip Technology Inc. ...
Page 65
... V DD Trap Conflict Illegal Opcode Uninitialized W Register © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Any active source of Reset will make the SYSRST sig- nal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...
Page 66
... SWDTEN bit setting. DS70175H-page 64 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 R/W-0 — — VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 67
... Clock Source Determinant POR Oscillator Configuration bits (FNOSC<2:0>) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTR SWR © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Setting Event Trap conflict event Illegal opcode or uninitialized W register access MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction ...
Page 68
... Oscillator Control register, OSCCON, depends on the type of Reset and the programmed values of the oscillator Configuration bits in the FOSC Configuration register. FSCM Notes Delay — FSCM FSCM LOCK FSCM — 3 — 3 — 3 — 3 — 3 — auto- FSCM © 2009 Microchip Technology Inc. ...
Page 69
... PIC24HJXXXGPX06/X08/X10 devices implement unique interrupts and 5 nonmaskable traps. These are summarized in Table 7-1 and Table 7-2. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 7.1.1 ALTERNATE VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1 ...
Page 70
... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70175H-page 68 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) © 2009 Microchip Technology Inc. ...
Page 71
... Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 AIVT Address 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C DMA0 – DMA Channel 0 0x00011E IC2 – ...
Page 72
... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Trap Reserved Reserved © 2009 Microchip Technology Inc. ...
Page 73
... The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...
Page 74
... IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 U-0 PSV — — bit 0 ‘1’ = Bit is set © 2009 Microchip Technology Inc. ...
Page 75
... Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — ...
Page 76
... Interrupt on positive edge DS70175H-page 74 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 INT4EP INT3EP INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 77
... DMA01IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF ...
Page 78
... Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70175H-page 76 © 2009 Microchip Technology Inc. ...
Page 79
... AD2IF: ADC2 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 T5IF T4IF ...
Page 80
... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70175H-page 78 © 2009 Microchip Technology Inc. ...
Page 81
... DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 C1IF: ECAN1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 OC8IF OC7IF ...
Page 82
... Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70175H-page 80 © 2009 Microchip Technology Inc. ...
Page 83
... SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 T7IF: Timer7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — ...
Page 84
... Unimplemented: Read as ‘0’ DS70175H-page 82 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-0 DMA6IF — U2EIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 U-0 U1EIF — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 85
... DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE ...
Page 86
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70175H-page 84 © 2009 Microchip Technology Inc. ...
Page 87
... AD2IE: ADC2 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 ...
Page 88
... Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70175H-page 86 © 2009 Microchip Technology Inc. ...
Page 89
... DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 C1IE: ECAN1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 OC8IE OC7IE ...
Page 90
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70175H-page 88 © 2009 Microchip Technology Inc. ...
Page 91
... SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 T7IE: Timer7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — R/W-0 ...
Page 92
... Unimplemented: Read as ‘0’ DS70175H-page 90 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-0 DMA6IE — U2EIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 U-0 U1EIE — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 93
... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 94
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175H-page 92 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC2IP<2:0> bit 8 R/W-0 R/W-0 DMA0IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 95
... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 96
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175H-page 94 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 DMA1IP<2:0> bit 8 R/W-0 R/W-0 U1TXIP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 97
... Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — ...
Page 98
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175H-page 96 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC7IP<2:0> bit 8 R/W-0 R/W-0 INT1IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 99
... Unimplemented: Read as ‘0’ bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 100
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175H-page 98 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2RXIP<2:0> bit 8 R/W-0 R/W-0 T5IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 101
... Unimplemented: Read as ‘0’ bit 2-0 SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 102
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175H-page 100 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC4IP<2:0> bit 8 R/W-0 R/W-0 DMA3IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 103
... Unimplemented: Read as ‘0’ bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 104
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175H-page 102 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 DMA4IP<2:0> bit 8 R/W-0 R/W-0 OC8IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 105
... Unimplemented: Read as ‘0’ bit 2-0 T7IP<2:0>: Timer7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 106
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175H-page 104 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 INT4IP<2:0> bit 8 R/W-0 R/W-0 T9IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 107
... Unimplemented: Read as ‘0’ bit 2-0 C2IP<2:0>: ECAN2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — U-0 ...
Page 108
... Unimplemented: Read as ‘0’ DS70175H-page 106 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 109
... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...
Page 110
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175H-page 108 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 C1TXIP<2:0> bit 8 R/W-0 R/W-0 DMA6IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 111
... Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 1111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 R-0 R-0 — R-0 R-0 R-0 VECNUM< ...
Page 112
... Note that only user interrupts with a priority level less can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to dis- able interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. © 2009 Microchip Technology Inc. ...
Page 113
... ADC1 ADC2 ECAN1 Reception ECAN1 Transmission ECAN2 Reception ECAN2 Transmission © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 The DMA controller features eight identical data transfer channels. Each channel has its own set of control and status registers. Each DMA channel can be configured to copy data either from buffers stored in dual port DMA RAM to peripheral SFRs, or from peripheral SFRs to buffers in DMA RAM ...
Page 114
... An additional pair of status registers, DMACS0 and DMACS1 are common to all DMAC channels. DS70175H-page 112 Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2009 Microchip Technology Inc. ...
Page 115
... MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 U-0 HALF NULLW — ...
Page 116
... U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) (2) (2) IRQSEL4 IRQSEL3 IRQSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) U-0 U-0 — — — bit 8 R/W-0 R/W-0 (2) (2) (2) IRQSEL1 IRQSEL0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 117
... R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 STA<15:8> R/W-0 R/W-0 R/W-0 STA<7:0> Unimplemented bit, read as ‘0’ ...
Page 118
... U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (2) CNT<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 (2) CNT<9:8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 119
... XWCOL5: Channel 5 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 ...
Page 120
... Write collision detected write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected DS70175H-page 118 © 2009 Microchip Technology Inc. ...
Page 121
... PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 R-1 R-1 — R-0 R-0 R-0 ...
Page 122
... DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits DS70175H-page 120 R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 123
... SOSCI Note 1: See Figure 9-2 for PLL details the Oscillator is used with modes, an extended parallel resistor with the value of 1 MΩ must be connected. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 • An on-chip PLL to scale the internal operating frequency to the required system clock frequency • ...
Page 124
... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F ’ is given by: OSC EQUATION 9-2: F OSC OSC © 2009 Microchip Technology Inc. is divided OSC ) and the defines the OSC ------------- = 2 ’ ...
Page 125
... Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 EQUATION 9-3: F ------------- 0.8-8.0 MHz ...
Page 126
... PLL modes. DS70175H-page 124 (1) R-0 U-0 R/W-y — NOSC<2:0> U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) © 2009 Microchip Technology Inc. R/W-y R/W-y (2) bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Clear only bit x = Bit is unknown ...
Page 127
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 (1) ...
Page 128
... Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70175H-page 126 R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...
Page 130
... FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. DS70175H-page 128 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 131
... COSC status bits with the new value of the NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 valid clock switch has been initiated, the LOCK (OSCCON< ...
Page 132
... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175H-page 130 © 2009 Microchip Technology Inc. ...
Page 133
... EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 10.2 Instruction-Based Power-Saving Modes PIC24HJXXXGPX06/X08/X10 devices have two spe- cial power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 134
... If a PMD bit is set, the corresponding mod- ule is disabled after a delay of 1 instruction cycle. Similarly PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). © 2009 Microchip Technology Inc. ...
Page 135
... SPI2 module is enabled bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 C2MD: ECAN2 Module Disable bit 1 = ECAN2 module is disabled 0 = ECAN2 module is enabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 U-0 T2MD T1MD — R/W-0 R/W-0 ...
Page 136
... PIC24HJXXXGPX06/X08/X10 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled DS70175H-page 134 © 2009 Microchip Technology Inc. ...
Page 137
... OC6MD: Output Compare 6 Module Disable bit 1 = Output Compare 6 module is disabled 0 = Output Compare 6 module is enabled bit 4 OC5MD: Output Compare 5 Module Disable bit 1 = Output Compare 5 module is disabled 0 = Output Compare 5 module is enabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 IC5MD IC4MD IC3MD ...
Page 138
... Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70175H-page 136 © 2009 Microchip Technology Inc. ...
Page 139
... Unimplemented: Read as ‘0’ bit 1 I2C2MD: I2C2 Module Disable bit 1 = I2C2 module is disabled 0 = I2C2 module is enabled bit 0 AD2MD: AD2 Module Disable bit 1 = AD2 module is disabled 0 = AD2 module is enabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 U-0 T6MD — — U-0 ...
Page 140
... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175H-page 138 © 2009 Microchip Technology Inc. ...
Page 141
... WR PORT CK Data Latch Read LAT Read Port © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 When a peripheral is enabled and actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port ...
Page 142
... Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. ; Configure PORTB<15:8> as inputs ; and PORTB<7:0> as outputs ; Delay 1 cycle ; Next Instruction capable of detecting input © 2009 Microchip Technology Inc. ...
Page 143
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Figure 12-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the TCKPS< ...
Page 144
... Unimplemented: Read as ‘0’ DS70175H-page 142 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 145
... T5CON, T6CON, T7CON, T8CON and T9CON regis- ters. T2CON, T4CON, T6CON and T8CON are shown in generic form in Register 13-1. T3CON, T5CON, T7CON and T9CON are shown in Register 13-2. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 For 32-bit timer/counter operation, Timer2, Timer4, Timer6 or Timer8 is the least significant word; Timer3, Timer5, Timer7 or Timer9 is the most significant word of the 32-bit timers ...
Page 146
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70175H-page 144 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2009 Microchip Technology Inc. ...
Page 147
... FIGURE 13-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 1x Gate Sync TMR2 Sync Comparator PR2 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70175H-page 145 ...
Page 148
... Note 1: The TxCK pin is not available for all timers. Refer to the “Pin Diagrams” section for the available pins. DS70175H-page 146 U-0 U-0 — — R/W-0 R/W-0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (1) — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 149
... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 3: The TyCK pin is not available for all timers. Refer to the “Pin Diagrams” section for the available pins. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 ...
Page 150
... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175H-page 148 © 2009 Microchip Technology Inc. ...
Page 151
... ICM<2:0> (ICxCON<2:0>) 3 Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 2. Capture timer value on every edge (rising and falling) 3. Prescaler Capture Event modes ...
Page 152
... Note 1: Timer selections may vary. Refer to the device data sheet for details. DS70175H-page 150 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... An ‘x’ signal, register or bit name denotes the number of the output compare channels. 2: The OCFA pin controls OC1 through OC4. The OCFB pin controls OC5 through OC8. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 The state of the output pin changes when the timer value matches the Compare register value ...
Page 154
... OCx rising and falling edge OCx falling edge 0 OCx falling edge 0 ‘0’, if OCxR is zero No interrupt ‘1’, if OCxR is non-zero ‘0’, if OCxR is zero OCFA falling edge for OC1 to OC4 ‘1’, if OCxR is non-zero Timer is Reset on Period Match © 2009 Microchip Technology Inc. — ...
Page 155
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — ...
Page 156
... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175H-page 154 © 2009 Microchip Technology Inc. ...
Page 157
... SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Each SPI module consists of a 16-bit shift register, SPIxSR (where 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates various status conditions ...
Page 158
... Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. DS70175H-page 156 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 159
... Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 ...
Page 160
... Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70175H-page 158 (2) (2) © 2009 Microchip Technology Inc. ...
Page 161
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: Read as ‘0’ This bit must not be set to ‘1’ by the user application. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — ...
Page 162
... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175H-page 160 © 2009 Microchip Technology Inc. ...
Page 163
... C slave operation with 10-bit address 2 • master operation with 7 or 10-bit address For details about the communication sequence in each of these modes, please refer to the “PIC24H Family Reference Manual”. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 2 17 Registers I2CxCON and I2CxSTAT are control and status registers, respectively ...
Page 164
... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2009 Microchip Technology Inc. ...
Page 165
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...
Page 166
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS70175H-page 164 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master master) © 2009 Microchip Technology Inc. ...
Page 167
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 R/C-0 HS — ...
Page 168
... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70175H-page 166 2 C slave device address byte. © 2009 Microchip Technology Inc. ...
Page 169
... AMSKx: Mask for Address Bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — ...
Page 170
... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175H-page 168 © 2009 Microchip Technology Inc. ...
Page 171
... UART1 or UART2 transmission or reception DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> and URXISEL<1:0> = 00). © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 • Hardware Flow Control Option with UxCTS and UxRTS pins • ...
Page 172
... DS70175H-page 170 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 173
... Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 MODE REGISTER (CONTINUED) ...
Page 174
... U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR C = Clear only bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 175
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 STATUS AND CONTROL REGISTER (CONTINUED) x ...
Page 176
... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175H-page 174 © 2009 Microchip Technology Inc. ...
Page 177
... Programmable clock source • Programmable link to input capture module (IC2 for both CAN1 and CAN2) for time-stamping and © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 network synchronization • Low-power Sleep and Idle mode The CAN bus module consists of a protocol engine and message buffering/control ...
Page 178
... RXF11 Filter RXF10 Filter RXF9 Filter RXF8 Filter RXF7 Filter RXF6 Filter RXF5 Filter RXF4 Filter RXF3 Filter RXF2 Filter RXF1 Filter RXF0 Filter Buffer RXM2 Mask RXM1 Mask RXM0 Mask Control CPU Configuration Bus Logic Interrupts © 2009 Microchip Technology Inc. ...
Page 179
... The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2<14>) enables or disables the filter. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Note: Typically, if the CAN module is allowed to transmit in a particular mode of operation ...
Page 180
... Use buffer window DS70175H-page 178 R/W-0 r-0 R/W-1 ABAT — U-0 R/W-0 U-0 — CANCAP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 REQOP<2:0> bit 8 U-0 R/W-0 — WIN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 181
... DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> • • • 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — ...
Page 182
... TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70175H-page 180 R-0 R-0 R-0 FILHIT<4:0> R-0 R-0 R-0 ICODE<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 183
... Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = RB31 buffer 11110 = RB30 buffer • • • 00001 = TRB1 buffer 00000 = TRB0 buffer © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 FSA< ...
Page 184
... TRB1 buffer 000000 = TRB0 buffer DS70175H-page 182 R-0 R-0 R-0 FBP<5:0> R-0 R-0 R-0 FNRB<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 185
... Unimplemented: Read as ‘0’ bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit bit 1 RBIF: RX Buffer Interrupt Flag bit bit 0 TBIF: TX Buffer Interrupt Flag bit © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R-0 R-0 R-0 TXBP RXBP TXWAR U-0 ...
Page 186
... TBIE: TX Buffer Interrupt Enable bit DS70175H-page 184 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — FIFOIE RBOVIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 RBIE TBIE bit Bit is unknown ...
Page 187
... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R-0 R-0 R-0 TERRCNT<7:0> R-0 R-0 R-0 RERRCNT<7:0> Unimplemented bit, read as ‘0’ ...
Page 188
... Q DS70175H-page 186 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 BRP<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared CAN CAN CAN CAN U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 189
... Bus line is sampled once at the sample point bit 5-3 SEG1PH<2:0>: Phase Buffer Segment 1 bits 111 = Length 000 = Length bit 2-0 PRSEG<2:0>: Propagation Time Segment bits 111 = Length 000 = Length © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 — — R/W-x R/W-x SEG1PH<2:0> ...
Page 190
... R/W-0 R/W-0 F2BP<3:0> R/W-0 R/W-0 R/W-0 F0BP<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 FLTEN9 FLTEN8 bit 8 R/W-1 R/W-1 FLTEN1 FLTEN0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 191
... F11BP<3:0>: RX Buffer Written when Filter 11 Hits bits bit 11-8 F10BP<3:0>: RX Buffer Written when Filter 10 Hits bits bit 7-4 F9BP<3:0>: RX Buffer Written when Filter 9 Hits bits bit 3-0 F8BP<3:0>: RX Buffer Written when Filter 8 Hits bits © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W Unimplemented bit, read as ‘ ...
Page 192
... F12BP<3:0>: RX Buffer Written when Filter 12 Hits bits DS70175H-page 190 R/W-0 R/W-0 R/W-0 F14BP<3:0> R/W-0 R/W-0 R/W-0 F12BP<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 193
... Value at POR ‘1’ = Bit is set bit 15-0 EID<15:0>: Extended Identifier bits 1 = Message address bit EIDx must be ‘1’ to match filter 0 = Message address bit EIDx must be ‘0’ to match filter © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-x R/W-x R/W-x SID7 SID6 ...
Page 194
... Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask DS70175H-page 192 R/W-0 R/W-0 R/W-0 F5MSK<1:0> R/W-0 R/W-0 R/W-0 F1MSK<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 F4MSK<1:0> bit 8 R/W-0 R/W-0 F0MSK<1:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 195
... F10MSK<1:0>: Mask Source for Filter 10 bit (same values as bit 15-14) bit 3-2 F9MSK<1:0>: Mask Source for Filter 9 bit (same values as bit 15-14) bit 1-0 F8MSK<1:0>: Mask Source for Filter 8 bit (same values as bit 15-14) © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 F13MSK< ...
Page 196
... EID4 EID3 EID2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x SID4 SID3 bit 8 R/W-x R/W-x EID17 EID16 bit Bit is unknown R/W-x R/W-x EID9 EID8 bit 8 R/W-x R/W-x EID1 EID0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 197
... C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 RXFUL<31:16>: Receive Buffer n Full bits 1 = Buffer is full (set by module Buffer is empty (clear by application software) © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/C-0 R/C-0 R/C-0 RXFUL12 RXFUL11 RXFUL10 R/C-0 ...
Page 198
... RXOVF20 RXOVF19 RXOVF18 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/C-0 R/C-0 RXOVF9 RXOVF8 bit 8 R/C-0 R/C-0 RXOVF1 RXOVF0 bit Bit is unknown R/C-0 R/C-0 RXOVF25 RXOVF24 bit 8 R/C-0 R/C-0 RXOVF17 RXOVF16 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 199
... When a remote transmit is received, TXREQ will be unaffected bit 1-0 TXmPRI<1:0>: Message Transmission Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority Note 1: This bit is cleared when TXREQ is set. © 2009 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R-0 R/W-0 R/W-0 TXERRn TXREQn RTRENn ...
Page 200
... EID10 EID9 EID8 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x SID7 SID6 bit 8 R/W-x R/W-x SRR IDE bit Bit is unknown R/W-x R/W-x EID15 EID14 bit 8 R/W-x R/W-x EID7 EID6 bit Bit is unknown © 2009 Microchip Technology Inc. ...