PIC24HJ128GP206-I/PT Microchip Technology, PIC24HJ128GP206-I/PT Datasheet - Page 115
![IC PIC MCU FLASH 64KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24HJ128GP206-I/PT
Manufacturer Part Number
PIC24HJ128GP206-I/PT
Description
IC PIC MCU FLASH 64KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
6.PIC24HJ128GP206-IPT.pdf
(286 pages)
7.PIC24HJ128GP306-IPT.pdf
(288 pages)
Specifications of PIC24HJ128GP206-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (43K x 24)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
13
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
18-ch x 12-bit
Controller Family/series
PIC24
No. Of I/o's
53
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ128GP206-I/PT
Manufacturer:
SMSC
Quantity:
7 600
Company:
Part Number:
PIC24HJ128GP206-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24HJ128GP206-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
7.2.1
Each DMA channel can be configured to transfer
words or bytes. As usual, words can only be moved to
and from aligned (even) addresses. Bytes can be
moved to or from any (legal) address.
If the SIZE bit (DMAxCON<14>) is clear, word sized
data is transferred. The LSb of the DMA RAM Address
register (DMAxSTA or DMAxSTB) is ignored. If
Post-Increment Addressing mode is enabled, the DMA
RAM Address register is incremented by 2 after every
word transfer.
If the SIZE bit is set, byte sized data is transferred. If
Post-Increment Addressing is enabled, the DMA RAM
Address register is incremented by 1 after every byte
transfer.
7.2.2
The DMAC supports Register Indirect and Register
Indirect Post-Increment Addressing modes for DMA
RAM addresses (source or destination). Each channel
can select the DMA RAM Addressing mode indepen-
dently. The Peripheral SFR is always accessed using
Register Indirect Addressing.
If the AMODE<1:0> bits (DMAxCON<5:4>) are set to
‘01’,
Post-Increment is used, which implies that the DMA
RAM address remains constant.
If the AMODE<1:0> bits are clear, DMA RAM is
accessed using Register Indirect Addressing with
Post-Increment, which means the DMA RAM address
will be incremented after every access.
© 2006 Microchip Technology Inc.
Note:
Register
BYTE OR WORD TRANSFER
DMAxCNT value is independent of data
transfer size (byte/word). If an address off-
set is required, a 1-bit left shift of the
counter is required to generate the correct
offset for (aligned) word transfers.
ADDRESSING MODES
Indirect
Addressing
without
Preliminary
Any DMA channel can be configured to operate in
Peripheral Indirect Addressing mode by setting the
AMODE<1:0> bits to ‘10’. In this mode, the DMA RAM
source or destination address is partially derived from
the peripheral as well as the DMA Address registers.
Each peripheral module has a pre-assigned peripheral
indirect address which is logically ORed with the DMA
Start Address register to obtain the effective DMA RAM
address. The DMA RAM Start Address register value
must be aligned to a power-of-two boundary.
7.2.3
Each DMA channel can be configured to transfer data
from a peripheral to DMA RAM, or from DMA RAM to a
peripheral.
If the DIR bit (DMAxCON<13>) is clear, the reads
occur from a peripheral SFR (using the DMA Periph-
eral Address register, DMAxPAD) and the writes are
directed to the DMA RAM (using the DMA RAM
Address register).
If the DIR bit (DMAxCON<13>) is set, the reads occur
from the DMA RAM (using the DMA RAM Address
register) and the writes are directed to the peripheral
(using
DMAxPAD).
7.2.4
If the NULLW bit (DMAxCON<11>) is set, a null data
write to the peripheral SFR is performed in addition to
a data transfer from the peripheral SFR to DMA RAM
(assuming the DIR bit is clear). This mode is most use-
ful in applications in which sequential reception of data
is required without any data transmission.
Note:
the
Only the ECAN and A/D modules can
utilize Peripheral Indirect Addressing.
DMA TRANSFER DIRECTION
NULL DATA PERIPHERAL WRITE
MODE
DMA
Peripheral
PIC24H
DS70175C-page 113
Address
register,