PIC16LF873A-I/SS Microchip Technology, PIC16LF873A-I/SS Datasheet - Page 32

• Manufacturer Part Number: PIC16LF873A-I/SS
• Description: IC MCU FLASH 4KX14 EE A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF873A-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Data Rom Size: 128 B
• Height: 1.75 mm
• Length: 10.2 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 5.3 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16LF873AI/SS

PIC16F87XA
2.3
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register which is a readable
and writable register. The upper bits (PC<12:8>) are
not readable, but are indirectly writable through the
PCLATH register. On any Reset, the upper bits of the
PC will be cleared. Figure 2-5 shows the two situations
for the loading of the PC. The upper example in the
figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0>
figure shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3>
FIGURE 2-5:
2.3.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
application note, AN556, “Implementing a Table Read”
(DS00556).
2.3.2
The PIC16F87XA family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POP’ed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS39582B-page 30
PC
PC
12
12 11 10
2
PCL and PCLATH
5
PCH
PCLATH<4:3>
PCH
COMPUTED GOTO
STACK
PCLATH
PCLATH<4:0>
8
PCLATH
8
7
PCH). The lower example in the
7
LOADING OF PC IN
DIFFERENT SITUATIONS
PCL
PCL
11
8
PCH).
0
0
Instruction with
PCL as
Destination
ALU
GOTO,CALL
Opcode <10:0>
2.4
All PIC16F87XA devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the user must ensure that the page select bits are
programmed so that the desired program memory
page is addressed. If a return from a CALL instruction
(or interrupt) is executed, the entire 13-bit PC is popped
off
PCLATH<4:3> bits is not required for the RETURN
instructions (which POPs the address from the stack).
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
EXAMPLE 2-1:
SUB1_P1
Note:
Note 1: There are no status bits to indicate stack
the
2: There are no instructions/mnemonics
Program Memory Paging
stack.
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3
CALL SUB1_P1
:
:
ORG 0x900
:
:
RETURN
The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH regis-
ter for any subsequent subroutine calls or
GOTO instructions.
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW and RETFIE instructions
or the vectoring to an interrupt address.
Therefore,
IN PAGE 1 FROM PAGE 0
CALL OF A SUBROUTINE
 2003 Microchip Technology Inc.
;Select page 1
;(800h-FFFh)
;Call subroutine in
;page 1 (800h-FFFh)
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
;return to
;Call subroutine
;in page 0
;(000h-7FFh)
manipulation
of
the