DSPIC33FJ128GP202-I/MM Microchip Technology, DSPIC33FJ128GP202-I/MM Datasheet - Page 291
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DSPIC33FJ128GP202-I/MM
Manufacturer Part Number
DSPIC33FJ128GP202-I/MM
Description
IC DSPIC MCU/DSP 128K 28-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ128GP202-I/MM
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
28-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 291 of 402
- Download datasheet (3Mb)
26.0
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communi-
cate with a wide variety of parallel devices, such as
communication peripherals, LCDs, external memory
FIGURE 26-1:
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Note 1: This data sheet summarizes the features
Parallel Master Port
Note 1: 28-pin devices do not have PMA<10:2>.
2: Some registers and associated bits
PARALLEL MASTER PORT
(PMP)
dsPIC33F
of
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 35. Parallel Master
Port
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
the
(PMP)”
PMP MODULE OVERVIEW
dsPIC33FJ32GP302/304,
(DS70299)
PMA<0>
PMALL
PMA<1>
PMALH
PMA<10:2>
PMCS1
PMBE
PMRD
PMRD/PMWR
PMWR
PMENB
PMD<7:0>
PMA<7:0>
PMA<10:8>
PMA<14>
of
and
the
Preliminary
(1)
Microcontroller
devices and microcontrollers. Because the interface
to parallel peripherals varies significantly, the PMP is
highly configurable.
Key features of the PMP module include:
• Fully multiplexed address/data mode
• Demultiplexed or partially multiplexed address/
• One Chip Select Line
• Programmable Strobe Options
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
• Programmable Wait States
• Selectable Input Voltage Levels
data mode
- up to 11 address lines with single chip select
- up to 12 address lines without chip select
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
Up to 11-Bit Address
8-Bit Data
LCD
Address Bus
Data Bus
Control Lines
Buffer
FIFO
DS70292D-page 291
EEPROM
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