DSPIC33FJ32MC304-E/ML Microchip Technology, DSPIC33FJ32MC304-E/ML Datasheet - Page 134
![IC DSPIC MCU/DSP 32K 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ32MC304-E/ML
Manufacturer Part Number
DSPIC33FJ32MC304-E/ML
Description
IC DSPIC MCU/DSP 32K 44-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ32MC304-E/ML
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
44-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
4 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM330021, MA330018
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC304-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
DSPIC33FJ32MC304-E/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 134 of 424
- Download datasheet (6Mb)
The DMA controller features eight identical data
transfer channels.
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
The DMA controller supports the following features:
• Eight DMA channels
• Register Indirect With Post-increment Addressing
• Register Indirect Without Post-increment
• Peripheral Indirect Addressing mode (peripheral
• CPU interrupt after half or full block transfer
FIGURE 8-1:
DS70291D-page 134
mode
Addressing mode
generates destination address)
complete
SRAM
Note:
SRAM X-Bus
CPU
CPU and DMA address buses are not shown for clarity.
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
PORT 1
DMA RAM
CPU Peripheral DS Bus
Peripheral
Non-DMA
PORT 2
Ready
DMA DS Bus
Preliminary
DMA Controller
• Byte or word transfers
• Fixed priority channel arbitration
• Manual (software) or Automatic (peripheral DMA
• One-Shot or Auto-Repeat block transfer modes
• Ping-Pong mode (automatic switch between two
• DMA request for each channel can be selected
• Debug support features
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
requests) transfer initiation
DPSRAM start addresses after each block
transfer complete)
from any supported interrupt source
Channels
DMA
Peripheral Indirect Address
Peripheral 1
CPU
Ready
DMA
© 2009 Microchip Technology Inc.
DMA
Peripheral 3
CPU
Ready
DMA
DMA
Peripheral 2
CPU
Ready
DMA
DMA
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