DSPIC33FJ32MC304-E/ML Microchip Technology, DSPIC33FJ32MC304-E/ML Datasheet - Page 168
![IC DSPIC MCU/DSP 32K 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ32MC304-E/ML
Manufacturer Part Number
DSPIC33FJ32MC304-E/ML
Description
IC DSPIC MCU/DSP 32K 44-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ32MC304-E/ML
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
44-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
4 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM330021, MA330018
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC304-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
DSPIC33FJ32MC304-E/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 168 of 436
- Download datasheet (6Mb)
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
11.6.3
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
11.6.3.1
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the reg-
isters remain unchanged. To change these registers,
they must be unlocked in hardware. The register lock is
controlled by the IOLOCK bit (OSCCON<6>). Setting
IOLOCK prevents writes to the control registers;
clearing IOLOCK allows writes.
To set or clear the IOLOCK bit, a specific command
sequence must be executed:
1.
2.
3.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
DS70291E-page 168
Note:
Write 0x46 to OSCCON<7:0>.
Write 0x57 to OSCCON<7:0>.
Clear (or set) the IOLOCK bit as a single
operation.
CONTROLLING CONFIGURATION
CHANGES
MPLAB
language functions for unlocking the
OSCCON register:
See MPLAB IDE Help for more
information.
Control Register Lock
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
®
C30
provides
built-in
C
11.6.3.2
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a configuration mismatch Reset is
triggered.
11.6.3.3
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY Con-
figuration bit (FOSC<5>) blocks the IOLOCK bit from
being cleared after it has been set once. If IOLOCK
remains set, the register unlock procedure does not
execute, and the peripheral pin select control registers
cannot be written to. The only way to clear the bit and
re-enable peripheral remapping is to perform a device
Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
peripheral pin select registers.
Continuous State Monitoring
Configuration Bit Pin Select Lock
© 2011 Microchip Technology Inc.
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