DSPIC33FJ32MC304-E/ML Microchip Technology, DSPIC33FJ32MC304-E/ML Datasheet - Page 145
![IC DSPIC MCU/DSP 32K 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ32MC304-E/ML
Manufacturer Part Number
DSPIC33FJ32MC304-E/ML
Description
IC DSPIC MCU/DSP 32K 44-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ32MC304-E/ML
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
44-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
4 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM330021, MA330018
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC304-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
DSPIC33FJ32MC304-E/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 145 of 436
- Download datasheet (6Mb)
9.0
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 oscillator system
provides:
FIGURE 9-1:
© 2011 Microchip Technology Inc.
SOSCO
SOSCI
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Note 1: This data sheet summarizes the features
Note 1:
R
(2)
2: Some registers and associated bits
OSCILLATOR CONFIGURATION
2:
3:
OSC1
OSC2
Secondary Oscillator
of
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Section 39. Oscillator
(Part III)” (DS70216) of the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
See
If the Oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 MΩ must be connected.
The term F
document F
is used in any ratio other than 1:1, which is the default.
Primary Oscillator
Oscillator
Oscillator
TUN<5:0>
Figure 9-2
LPRC
FRC
POSCMD<1:0>
the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/
X04 OSCILLATOR SYSTEM DIAGRAM
P
LPOSCEN
CY
refers to the clock source for all the peripherals, while F
and F
for PLL details.
dsPIC33FJ32MC302/304,
Auxiliary Oscillator
P
are used interchangeably, except in the case of Doze mode. F
POSCCLK
S1
S3
÷ 16
family
FRCDIV<2:0>
AOSCMD<1:0>
POSCCLK
and
AOSCCLK
of
in
PLL
ASRCSEL
• External and internal oscillator options as clock
• An on-chip Phase-Locked Loop (PLL) to scale the
• An internal FRC oscillator that can also be used
• Clock switching between various clock sources
• Programmable clock postscaler for system power
• A Fail-Safe Clock Monitor (FSCM) that detects
• An Oscillator Control register (OSCCON)
• Non-volatile Configuration bits for main oscillator
• An auxiliary crystal oscillator for audio DAC
A simplified diagram of the oscillator system is shown
in
XTPLL, HSPLL,
ECPLL, FRCPLL
F
VCO (1)
Clock Fail
sources
internal operating frequency to the required
system clock frequency
with the PLL, thereby allowing full-speed
operation without any external clock generation
hardware
savings
clock failure and takes fail-safe measures
selection.
Figure
XT, HS, EC
FRCDIV16
CY
FRCDIVN
S7
refers to the clock source for the CPU. Throughout this
F
LPRC
S
9-1.
FRC
VCO
OSC
(1)
Clock Switch
S1/S3
S7
S6
S0
S5
S4
S2
P
SELACK
NOSC<2:0>
and F
CY
÷ 2
will be different when Doze mode
Reset
FNOSC<2:0>
DOZE<2:0>
÷ N
DS70291E-page 145
APSTSCLR<2:0>
ACLK
Timer1
WDT,
PWRT,
FSCM
DAC
F
F
F
OSC
CY (3)
P (3)
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