PIC16F767-I/SP Microchip Technology, PIC16F767-I/SP Datasheet - Page 67
![IC PIC MCU FLASH 8KX14 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16F767-I/SP
Manufacturer Part Number
PIC16F767-I/SP
Description
IC PIC MCU FLASH 8KX14 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F737-ISP.pdf
(276 pages)
4.PIC16F737-ISP.pdf
(10 pages)
Specifications of PIC16F767-I/SP
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
AUSART/CCP/I2C/MSSP/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
3
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF777 - BOARD DAUGHTER ICEPIC3
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F767-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F737-ISP PDF datasheet #3
- PIC16F737-ISP PDF datasheet #4
- Current page: 67 of 276
- Download datasheet (6Mb)
5.3
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 5-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings and to Section 16.1 “Read-Modify-
Write Operations” for additional information on
read-modify-write operations.
FIGURE 5-16:
2004 Microchip Technology Inc.
Port/Peripheral Select
Peripheral Data Out
Data Bus
WR
Port
WR
TRIS
RD
TRIS
Peripheral
OE
RD
Port
Peripheral Input
Note 1: I/O pins have diode protection to V
(3)
2: Port/Peripheral Select signal selects between port
3: Peripheral OE (Output Enable) is only activated if
PORTC and the TRISC Register
data and peripheral output.
Peripheral Select is active.
TRIS Latch
Data Latch
D
D
CK
CK
(2)
Q
Q
Q
Q
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>,
RC<7:5> PINS
0
1
Q
EN
D
DD
Schmitt
Trigger
and V
V
V
N
P
SS
DD
SS
.
I/O
pin
(1)
FIGURE 5-17:
Port/Peripheral Select
Peripheral Data Out
Data Bus
WR
Port
WR
TRIS
RD
TRIS
Peripheral
OE
RD
Port
SSPl Input
Note 1: I/O pins have diode protection to V
(3)
2: Port/Peripheral Select signal selects between port data
3: Peripheral OE (Output Enable) is only activated if
and peripheral output.
Peripheral Select is active.
TRIS Latch
Data Latch
D
D
CK
CK
(2)
Q
Q
Q
Q
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<4:3> PINS
0
1
PIC16F7X7
Q
SSPSTAT<6>
CKE
EN
D
Schmitt
Trigger
DS30498C-page 65
DD
and V
Vss
0
1
V
N
P
DD
SS
Schmitt
Trigger
with
SMBus
Levels
.
I/O
pin
(1)
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