PIC16F767-I/SP Microchip Technology, PIC16F767-I/SP Datasheet - Page 50
![IC PIC MCU FLASH 8KX14 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16F767-I/SP
Manufacturer Part Number
PIC16F767-I/SP
Description
IC PIC MCU FLASH 8KX14 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F737-ISP.pdf
(276 pages)
4.PIC16F737-ISP.pdf
(10 pages)
Specifications of PIC16F767-I/SP
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
AUSART/CCP/I2C/MSSP/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
3
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF777 - BOARD DAUGHTER ICEPIC3
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F767-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F737-ISP PDF datasheet #3
- PIC16F737-ISP PDF datasheet #4
- Current page: 50 of 276
- Download datasheet (6Mb)
PIC16F7X7
4.7.4
Any interrupt, such as WDT or INT0, will cause the part
to leave the Sleep mode.
The SCS bits are unaffected by a SLEEP command and
are the same before and after entering and leaving
Sleep. The clock source used after an exit from Sleep
is determined by the SCS bits.
4.7.4.1
If SCS<1:0> = 00:
1.
2.
3.
DS30498C-page 48
The device is held in Sleep until the CPU start-up
time-out is complete.
If the primary system clock is configured as an
external oscillator (HS, XT, LP), then the OST will
be active waiting for 1024 clocks of the primary
system clock. While waiting for the OST, the
device will be held in Sleep unless Two-Speed
Start-up is enabled. The OST and CPU start-up
timers run in parallel. Refer to Section 15.17.3
“Two-Speed Clock Start-up Mode” for details
on Two-Speed Start-up.
After both the CPU start-up timer and the
Oscillator Start-up Timer have timed out, the
device will exit Sleep and begin instruction
execution with the primary clock defined by the
FOSC bits.
EXITING SLEEP WITH AN
INTERRUPT
Sequence of Events
If SCS<1:0> = 01 or 10:
1.
2.
Note:
The device is held in Sleep until the CPU start-up
time-out is complete.
After the CPU start-up timer has timed out, the
device will exit Sleep and begin instruction
execution with the selected oscillator mode.
If a user changes SCS<1:0> just before
entering Sleep mode, the system clock
used when exiting Sleep mode could be
different than the system clock used when
entering Sleep mode.
As an example, if SCS<1:0> = 01, T1OSC
is the system clock and the following
instructions are executed:
BCF
SLEEP
then a clock change event is executed. If
the primary oscillator is XT, LP or HS, the
core will continue to run off T1OSC and
execute the SLEEP command.
When Sleep is exited, the part will resume
operation with the primary oscillator after
the OST has expired.
2004 Microchip Technology Inc.
OSCCON,SCS0
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