PIC16LF873A-I/SP Microchip Technology, PIC16LF873A-I/SP Datasheet - Page 39

• Manufacturer Part Number: PIC16LF873A-I/SP
• Description: IC MCU FLASH 4KX14 EE A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF873A-I/SP

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16LF
• No. Of I/o's: 22
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF873AI/SP

3.6
Flash program memory may only be written to if the
destination address is in a segment of memory that is
not write-protected, as defined in bits WRT1:WRT0 of
the device configuration word (Register 14-1). Flash
program memory must be written in four-word blocks. A
block consists of four words with sequential addresses,
with a lower boundary defined by an address, where
EEADR<1:0> = 00. At the same time, all block writes to
program memory are done as erase and write opera-
tions. The write operation is edge-aligned and cannot
occur across boundaries.
To write program data, it must first be loaded into the
buffer registers (see Figure 3-1). This is accomplished
by first writing the destination address to EEADR and
EEADRH and then writing the data to EEDATA and
EEDATH. After the address and data have been set up,
then the following sequence of events must be
executed:
1.
2.
3.
All four buffer register locations MUST be written to with
correct data. If only one, two or three words are being
written to in the block of four words, then a read from
the program memory location(s) not being written to
must be performed. This takes the data from the pro-
gram location(s) not being written and loads it into the
EEDATA and EEDATH registers. Then the sequence of
events to transfer data to the buffer registers must be
executed.
FIGURE 3-1:
 2003 Microchip Technology Inc.
EEADR<1:0> = 00
Set the EEPGD control bit (EECON1<7>).
Write 55h, then AAh, to EECON2 (Flash
programming sequence).
Set the WR control bit (EECON1<1>).
Writing to Flash Program Memory
First word of block
to be written
Buffer Register
BLOCK WRITES TO FLASH PROGRAM MEMORY
14
EEADR<1:0> = 01
7
Buffer Register
5
EEDATH
6
14
Program Memory
EEADR<1:0> = 10
0 7
To transfer data from the buffer registers to the program
memory, the EEADR and EEADRH must point to the last
location in the four-word block (EEADR<1:0> = 11).
Then the following sequence of events must be
executed:
1.
2.
3.
The user must follow the same specific sequence to ini-
tiate the write for each word in the program block, writ-
ing each program word in sequence (00,01,10,11).
When the write is performed on the last word
(EEADR<1:0> = 11), the block of four words are
automatically erased and the contents of the buffer
registers are written into the program memory.
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOP instructions after the WR
bit is set. Since data is being written to buffer registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operations for the typical 4 ms, only during the cycle in
which the erase takes place (i.e., the last word of the
four-word block). This is not Sleep mode as the clocks
and peripherals will continue to run. After the write
cycle, the processor will resume operation with the third
instruction after the EECON1 write instruction. If the
sequence is performed to any other location, the action
is ignored.
Set the EEPGD control bit (EECON1<7>).
Write 55h, then AAh, to EECON2 (Flash
programming sequence).
Set control bit WR (EECON1<1>) to begin the
write operation.
EEDATA
Buffer Register
8
14
EEADR<1:0> = 11
0
PIC16F87XA
Buffer Register
Four words of
Flash are erased,
then all buffers
are transferred
to Flash
automatically
after this word
is written
DS39582B-page 37
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