PIC16F84-04/P Microchip Technology, PIC16F84-04/P Datasheet - Page 678
![IC MCU FLASH 1KX14 EE 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F84-04/P
Manufacturer Part Number
PIC16F84-04/P
Description
IC MCU FLASH 1KX14 EE 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16LF84A-04P.pdf
(125 pages)
3.PIC16LF84A-04P.pdf
(4 pages)
Specifications of PIC16F84-04/P
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
68 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
13
Number Of Timers
1
Operating Supply Voltage
2 V to 6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F84-04/P
Manufacturer:
TI
Quantity:
201
Company:
Part Number:
PIC16F84-04/P
Manufacturer:
Microchip Technology
Quantity:
1 970
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PICmicro MID-RANGE MCU FAMILY
I
DS31035A-page 35-6
I
Inter-Integrated Circuit. This is a two wire communication interface. This feature is one of the
modes of the SSP module.
Indirect Addressing
When the Data Memory Address is not contained in the Instruction. The instruction operates on
the INDF address, which causes the Data Memory Address to be the value in the FSR register.
The execution of the instruction will always access the data at the address pointed to by the FSR
register.
Instruction Bus
The bus which is used to transfer instruction words from the program memory to the CPU.
Instruction Fetch
Due to the Harvard architecture, when one instruction is to be executed, the next location in pro-
gram memory is “fetched” and ready to be decoded as soon as the currently executing instruction
is completed.
Instruction cycle
The events for an instruction to execute. There are four events which can generally be described
as: Decode, Read, Execute, and Write. Not all events will be done by all instructions. To see the
operations during the instruction cycle, please look in the description of each instruction. Four
external clocks (Tosc) make one instruction cycle (T
Interrupt
A signal to the CPU that causes the program flow to be forced to the Interrupt Vector Address
(04h in program memory). Before the program flow is changed, the contents of the Program
Counter (PC) are forced onto the hardware stack, so that program execution may return to the
interrupted point.
INTRC
Internal Resistor-Capacitor (RC). Some devices have a device oscillator option that allows the
clock to come from an internal RC.
2
C
CY
).
1997 Microchip Technology Inc.
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