PIC16F84-04/P Microchip Technology, PIC16F84-04/P Datasheet - Page 450
![IC MCU FLASH 1KX14 EE 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F84-04/P
Manufacturer Part Number
PIC16F84-04/P
Description
IC MCU FLASH 1KX14 EE 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16LF84A-04P.pdf
(125 pages)
3.PIC16LF84A-04P.pdf
(4 pages)
Specifications of PIC16F84-04/P
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
68 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
13
Number Of Timers
1
Operating Supply Voltage
2 V to 6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
PIC16F84-04/P
Manufacturer:
TI
Quantity:
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Part Number:
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Manufacturer:
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PICmicro MID-RANGE MCU FAMILY
24.3.1
DS31024A-page 24-8
Slope A/D Timer (ADTMR)
The Slope A/D timer (ADTMR) is comprised of a 16-bit timer (ADTMRH:ADTMRL), which is
incremented every oscillator cycle. The ADTMR registers are cleared by a power-on reset; oth-
erwise the software must initialize it after each conversion. A separate 16-bit capture register
(ADCAPH:ADCAPL) is used to capture the ADTMR count if a Slope A/D capture event occurs
(see below). Both the Slope A/D timer and capture registers are readable and writable. The 16-bit
timer is a read/write register and is cleared on any device reset.
During a conversion one or both of the following events will occur:
• capture event
• timer overflow
In a capture event, the comparator trips when the slope voltage on the CDAC output exceeds the
input voltage from the selected Slope A/D channel, causing the comparator output to transition
from high to low. This causes a transfer of the current timer count to the capture register and sets
the ADCIF flag bit.
An interrupt will be generated if the ADCIE bit is set (interrupt enabled). In addition, GIE and PIE
bits must be set. Software is responsible for clearing the ADCIF flag bit prior to the next conver-
sion cycle. This interrupt can only occur once per conversion cycle.
In a timer overflow condition, the timer rolls over from FFFFh to 0000h, and a capture overflow
flag (OVFIF) is asserted. The timer continues to increment following a timer overflow. An interrupt
can be generated if bit OVFIE is set (interrupt enabled). In addition, the GIE and PIE bits must
be set. Software is responsible for clearing the OVFIF flag bit prior to the next conversion cycle.
Figure 24-2: Example Slope A/D Conversion Cycle
Note 1: Reading or writing the ADTMR register during an Slope A/D conversion cycle can
Note 2: The correct sequence for writing the ADTMR register is HI byte followed by LO byte.
produce unpredictable results and is not recommended.
Reversing this order will prevent the Slope A/D timer from running.
CAPTURE
CLK
ADRST
ADCON0<1>
CDAC
ADCIF
Capture
Register
ADTMR
COUNT
(must be cleared by software)
XX
ADTMR INCREMENTS
XX+1 XX+2 XX+3
XX
XX+8 XX+9
1997 Microchip Technology Inc.
COMPARE
XX+8
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