DSPIC30F3014-30I/ML Microchip Technology, DSPIC30F3014-30I/ML Datasheet
DSPIC30F3014-30I/ML
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DSPIC30F3014-30I/ML Summary of contents
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... Rev. A1 Silicon Errata The dsPIC30F3014/4013 (Rev. A1) samples that you have received were found to conform to the specifications and functionality described in the following documents: • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70138 – “dsPIC30F3014/4013 Data Sheet” • DS70046 – “dsPIC30F Family Reference Manual” ...
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... PLL Mode If 8x PLL mode is used, the input frequency range is 5 MHz-10 MHz instead of 4 MHz-10 MHz. 16. Low-Voltage Detect (LVD) The external Low-Voltage Detect (LVD) module is not connected to the AN2 Pad. 17. Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep ...
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... MAC class instructions not use the + = address modification not prefetch data from Y data space. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2. Module: CPU – Instruction DAW.b The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>), when executed ...
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... Table 1. The work around for Example 2 is demonstrated in Example 3. DS80228K-page 4 These instructions are identified in Table 1. Example 2 demonstrates one scenario where this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F3014/4013 devices. (1) (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 ...
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... X; \ DISICNT = 0; } DISI_PROTECT(SRbits.IPL = 0x5); © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Work around The user may disable interrupt nesting or execute a DISI instruction before modifying the CPU IPL or Interrupt 1 setting. A minimum DISI value required if the DISI is executed immediately before the CPU IPL or Interrupt 1 is modified, as shown in Example 4 ...
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... Module: DISI Instruction When a user executes a DISI #7, for example, this will disable interrupts from cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down from The counter is loaded with 7 at the end of the DISI instruction. ...
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... PORTF will be modified by a write to address 0x0E0 Work around User software should avoid writing to the unimplemented locations listed above. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 12. Module: 4x PLL Operation When the 4x PLL mode of operation is selected, . the specified input frequency range of 4-10 MHz is CY not fully supported ...
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... GotoSleep( ) function call. This ensures that the device continues executing the correct code sequence after waking up from Sleep mode. Example 8 demonstrates described above would apply to a dsPIC30F3014 device. the function call would be following the ...
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... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 ; Ensure flag is reset ; Return from Interrupt Service Routine Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... Status bit (OSCCON<3>). If this bit is clear, return from the trap service routine immediately and continue program execution. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 23. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This only occurs when using the following addressing modes: • ...
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... Module When the I C module is enabled by setting the I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates “Communication 2 Start” to all devices on the I C bus, and can cause a bus collision in a multi-master configuration ...
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... C), and 23 (Timer). Removed silicon issue 13 (Using OSC2/RC15 pin for Digital I/O). Revision K (9/2008) 2 Replaced issues 19 and with issue 26 (I Added silicon issues 22 (PLL Lock Status Bit), 23 (PSV 2 Operations) and 24-26 (I C). © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2 C), and 21 (I/O 2 C). DS80228K-page 13 ...
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... NOTES: DS80228K-page 14 © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...