DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F3010-20I/SP
• Description: IC DSPIC MCU/DSP 24K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-20I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301020ISP

dsPIC30F3010/3011
TABLE 2:
DS80449D-page 2
Power (LP)
Note 1:
Operations
Operations
Controller
Oscillator
Compare
Compare
Interrupt
Module
32 kHz
Output
Output
Low-
CPU
CPU
PSV
PSV
CPU
CPU
ADC
ADC
PLL
PLL
QEI
QEI
Only those issues indicated in the last column apply to the current silicon revision.
Sampling Rate
Termination of
Modification
Sleep Mode
Sleep Mode
PWM Mode
Index Pulse
Instructions
Nested DO
Generation
MAC Class
Instruction
Instruction
SILICON ISSUE SUMMARY
Using SR
4x Mode
8x Mode
Interrupt
Feature
Address
with ±4
DAW.b
Loops
Reset
DISI
Early
—
—
—
Number
Item
10.
12.
13.
14.
15.
16.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Sequential MAC instructions, which prefetch data from Y data
space using ±4 address modification, will cause an address
error trap.
The Decimal Adjust instruction, DAW.b, may improperly clear
the Carry bit, C (SR<0>).
In certain instructions, fetching one of the operands from
program memory using Program Space Visibility (PSV) will
corrupt specific bits in the STATUS Register, SR.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any PSV page.
The 4x PLL mode of operation may not function correctly for
certain input frequencies.
When using two DO loops in a nested fashion, terminating the
inner-level DO loop by setting the EDT bit (CORCON<11>) will
produce unexpected results.
An interrupt occurring immediately after modifying the CPU
IPL, interrupt IPL, interrupt enable, or interrupt flag may cause
an address error trap.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
The LP oscillator does not function when the device is placed
in Sleep mode.
Output compare will produce a glitch when loading 0% duty
cycle in PWM mode. It will also miss the next compare after
the glitch.
The output compare module will produce a glitch on the output
when an I/O pin is initially set high and the module is
configured to drive the pin low at a specified time.
The Index Pulse Reset mode of the QEI does not work
properly when used along with count error detection. When
counting upwards, the POSCNT register will increment one
extra count after the index pulse is received. The extra count
will generate a false count error interrupt.
ADC event triggers from the INT0 pin will not wake-up the
device from Sleep mode if the SMPI bits are non-zero.
If 8x PLL mode is used, the input frequency range is 5 MHz-10
MHz instead of 4 MHz-10 MHz.
The 10-bit Analog-to-Digital Converter (ADC) has a maximum
sampling rate of 750 ksps.
The QEI module does not generate an interrupt in a particular
overflow condition.
Issue Summary
© 2010 Microchip Technology Inc.
Revisions
A0 A1 A2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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(1)