PIC18F87J90-I/PT Microchip Technology, PIC18F87J90-I/PT Datasheet - Page 241
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PIC18F87J90-I/PT
Manufacturer Part Number
PIC18F87J90-I/PT
Description
IC PIC MCU FLASH 128KB 80-TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F67J90-IPT.pdf
(450 pages)
2.PIC18F67J90-IPT.pdf
(3 pages)
3.PIC18F67J90-IPT.pdf
(10 pages)
4.PIC18F66J90-IPT.pdf
(444 pages)
Specifications of PIC18F87J90-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
67
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3923 B
Interface Type
AUSART, EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
67
Number Of Timers
4
Operating Supply Voltage
2.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164323 - MODULE SKT FOR 100TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F87J90-I/PT
Manufacturer:
MICROCHIP
Quantity:
4 000
Company:
Part Number:
PIC18F87J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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18.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 18-19). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
FIGURE 18-19:
TABLE 18-3:
2010 Microchip Technology Inc.
2
C Master mode, the Baud Rate Generator (BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
BAUD RATE
F
CY
I
2
C™ CLOCK RATE w/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C Master mode, the BRG is
SSPM<3:0>
SCL
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
SSPM<3:0>
CY
* 2
) on the
Reload
Control
CLKO
Reload
PIC18F87J90 FAMILY
Table 18-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
18.4.7.1
When the device is operating in one of the
power-managed modes, the clock source to the BRG
may change frequency, or even stop, depending on the
mode and clock source selected. Switching to a Run or
Idle mode from either the secondary clock or internal
oscillator is likely to change the clock rate to the BRG.
In Sleep mode, the BRG will not be clocked at all.
BRG Down Counter
SSPADD<6:0>
BRG Value
0Ch
1Fh
18h
63h
09h
27h
02h
09h
00h
Baud Rate Generation in
Power-Managed Modes
F
OSC
(2 Rollovers of BRG)
/4
312.5 kHz
DS39933D-page 241
400 kHz
100 kHz
400 kHz
308 kHz
100 kHz
333 kHz
100 kHz
1 MHz
F
SCL
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