PIC18F87J90-I/PT Microchip Technology, PIC18F87J90-I/PT Datasheet - Page 144

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PIC18F87J90-I/PT

Manufacturer Part Number
PIC18F87J90-I/PT
Description
IC PIC MCU FLASH 128KB 80-TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F87J90-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
67
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3923 B
Interface Type
AUSART, EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
67
Number Of Timers
4
Operating Supply Voltage
2.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164323 - MODULE SKT FOR 100TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F87J90-I/PT
Manufacturer:
MICROCHIP
Quantity:
4 000
Part Number:
PIC18F87J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F87J90-I/PT
0
PIC18F87J90 FAMILY
12.1
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 12-1:
FIGURE 12-2:
DS39933D-page 144
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
T1OSO/T13CKI
Timer1 Operation
T1OSI
T1OSI
Timer1 Oscillator
Timer1 Oscillator
T1OSCEN
T1CKPS<1:0>
T1SYNC
TMR1ON
TIMER1 BLOCK DIAGRAM (8-BIT MODE)
T1OSCEN
T1CKPS<1:0>
T1SYNC
TMR1ON
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
(1)
(1)
TMR1CS
TMR1CS
Clear TMR1
(CCP Special Event Trigger)
Clear TMR1
(CCP Special Event Trigger)
Clock
F
Internal
Clock
Internal
F
OSC
OSC
/4
/4
On/Off
1
0
1
0
Timer1 Clock Input
Timer1 Clock Input
Prescaler
Prescaler
1, 2, 4, 8
1, 2, 4, 8
cycle (F
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
2
2
OSC
TMR1L
TMR1L
/4). When the bit is set, Timer1 increments
8
Synchronize
8
Synchronize
Sleep Input
Sleep Input
Detect
Detect
High Byte
High Byte
TMR1H
TMR1
TMR1
8
 2010 Microchip Technology Inc.
8
8
1
0
1
0
Set
TMR1IF
on Overflow
Read TMR1L
Write TMR1L
Internal Data Bus
Set
TMR1IF
on Overflow
Timer1
Timer1
On/Off
On/Off

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