PIC24FJ64GA002-E/ML Microchip Technology, PIC24FJ64GA002-E/ML Datasheet - Page 16
![IC PIC MCU FLASH 64K 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24FJ64GA002-E/ML
Manufacturer Part Number
PIC24FJ64GA002-E/ML
Description
IC PIC MCU FLASH 64K 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
4.PIC24FJ64GA004-EPT.pdf
(262 pages)
Specifications of PIC24FJ64GA002-E/ML
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240013, AC164127, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
8192Byte
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC24FJ64GA004 FAMILY
47. Module: SPI (Master Mode)
48. Module: SPI (Framed SPI Modes)
DS80470E-page 16
When operating in Enhanced Buffer Master mode,
the Transmit Buffer Full flag, SPITBF, may be
cleared before all data in the FIFO buffer has
actually been sent. This may result in data being
overwritten before it can be sent.
This has only been observed when the SPI clock
prescalers are configured for a divider of greater
than 1:4.
This behavior has not been observed when the
module is operating in any other mode.
Work around
Several options are available:
•
•
•
Affected Silicon Revisions
Framed SPI modes as described in the device data
sheet are not supported. When using the module,
verify the FRMEN bit (SPIxCON2<15>) is cleared.
All other SPI modes function as described.
Work around
None.
Affected Silicon Revisions
A3/
A3/
A4
A4
X
If possible, use a total clock prescale factor
of 1:4 or less.
Do not use SPITBF to indicate when new
data can be written to the buffer. Instead,
use the SPIRBF or SPIBEC flags to track
the number of bytes actually transmitted.
If the SPITBF flag must be used, always
wait at least one-half SPI clock cycle before
writing to the transmit buffer.
B4
B4
X
X
B5
B5
X
X
B8
B8
X
X
49. Module: Core (Data SRAM)
50. Module: I/O (PORTA and PORTB)
51. Module: A/D Converter
During
(addresses above the SFR space, starting at
0800h), the device’s baseline current consump-
tion (I
ously specified in the data sheet. This occurs
only with oscillator speeds of 1 MHz or slower,
regardless of the clock mode.
Work around
None.
Affected Silicon Revisions
PORTA pin, RA0, may not operate correctly as
an input when the open-drain output is enabled
for PORTB pin, RB0 (ODCB<0>). RA0 will
operate correctly as an output.
Work around
None.
Affected Silicon Revisions
Once
(AD1CON1<15> = 1), it may continue to draw
extra current even if the module is later disabled
(AD1CON1<15> = 0).
Work around
In addition to disabling the module through the
ADON bit, set the corresponding PMD bit
(ADC1MD, PMD1<0>) to power it down
completely.
Disabling the A/D module through the PMD reg-
ister also disables the AD1PCFG registers,
which in turn, affects the state of any port pins
with analog inputs. Users should consider the
effect on I/O ports and other digital peripherals
on those ports when ADC1MD is used for power
conservation.
Affected Silicon Revisions
A3/
A3/
A3/
A4
A4
A4
X
X
DD
B4
B4
B4
) may periodically be higher than previ-
X
X
X
the
any
B5
B5
B5
X
X
X
operations
A/D
2010 Microchip Technology Inc.
B8
B8
B8
X
X
module
to
data
is
enabled
SRAM