PIC24FJ64GA002-E/ML Microchip Technology, PIC24FJ64GA002-E/ML Datasheet - Page 13
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PIC24FJ64GA002-E/ML
Manufacturer Part Number
PIC24FJ64GA002-E/ML
Description
IC PIC MCU FLASH 64K 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
4.PIC24FJ64GA004-EPT.pdf
(262 pages)
Specifications of PIC24FJ64GA002-E/ML
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240013, AC164127, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
8192Byte
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
34. Module: RTCC
35. Module: SPI (Master Mode)
EXAMPLE 1:
2010 Microchip Technology Inc.
Under certain circumstances, the value of the
Alarm Repeat Counter (ALCFGRPT<7:0>) may be
unexpectedly decremented. This happens only
when a byte write to the upper byte of ALCFGRPT
is performed in the interval between a device POR/
BOR and the first edge from the RTCC clock
source.
Work around
Do not perform byte writes on ALCFGRPT,
particularly the upper byte.
Alternatively, wait until one period of the SOSC
has completed before performing byte writes to
ALCFGRPT.
Affected Silicon Revisions
In Master mode, the SPI Interrupt Flag (SPIxIF)
and the SPIRBF bit (SPIxSTAT<0>) may both
become set one-half clock cycle early, instead of
on the clock edge. This occurs only under the
following circumstances:
• Enhanced Buffer mode is disabled
• the module is configured for serial data output
If the application is using the interrupt flag to
determine when data to be transmitted is written to
the transmit buffer, the data currently in the buffer
may be overwritten.
Work around
Before writing to the SPI buffer, check the SCK pin
to determine if the last clock edge has passed.
Example 1
doing this. In this example, the RD1 pin functions as
the SPI clock, SCK, which is configured as Idle low.
Affected Silicon Revisions
while(IFS0bits.SPI1IF == 0){}
while(PORTDbits.RD1 == 1){}
SPI1BUF = 0xFF;
A3/
A3/
A4
A4
X
(SPIBEN = 0); and
changes on transition from clock active to clock
Idle state (CKE = 1).
X
B4
B4
X
(below) demonstrates a method for
B5
B5
X
CHECKING THE STATE OF SPIxIF AGAINST THE SPI CLOCK
B8
B8
//wait for the transmission to complete
//wait for the last clock to finish
//write new data to the buffer
PIC24FJ64GA004 FAMILY
36. Module: I
Under certain circumstances, a module operating
in Master mode may Acknowledge its own com-
mand addressed to a slave device. This happens
when the following occurs:
• 10-Bit Addressing mode is used (A10M = 1);
• the I
In these cases, the master also Acknowledges the
address command and generates an erroneous I
slave interrupt, as well as the I
Work around
Several options are available:
• When using 10-Bit Addressing mode, make
If this cannot be avoided:
• Clear the A10M bit (I2CxCON<10> = 0) prior to
• Read the ADD10 bit (I2CxSTAT<8>) to check
Affected Silicon Revisions
A3/
A4
and
address bits (I2CADD<9:8>) as the addressed
slave module.
certain that the master and slave devices do not
share the same 2 MSbs of their addresses.
performing a Master mode transmit.
for a full 10-bit match whenever a slave I
interrupt occurs on the master module.
X
2
C master has the same two upper
B4
X
2
C (Master Mode)
B5
X
B8
X
2
C master interrupt.
DS80470E-page 13
2
C
2
C