AT89C51RC2-RLRIM Atmel, AT89C51RC2-RLRIM Datasheet - Page 87
![IC MCU FLASH 8051 32K 5V 44-VQFP](/photos/6/92/69202/313-44-vqfp_sml.jpg)
AT89C51RC2-RLRIM
Manufacturer Part Number
AT89C51RC2-RLRIM
Description
IC MCU FLASH 8051 32K 5V 44-VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51RB2-RLTIL.pdf
(127 pages)
Specifications of AT89C51RC2-RLRIM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
AT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
AT89C51RC2RLRIMTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Flash Registers and
Memory Map
Hardware Register
Flash Memory Lock Bits
4180E–8051–10/06
The AT89C51RB2/RC2 Flash memory uses several registers for its management:
•
•
The only hardware register of the AT89C51RB2/RC2 is called Hardware Security Byte
(HSB).
Table 65. Hardware Security Byte (HSB)
Boot Loader Jump Bit (BLJB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
•
•
The three lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 66.
Number
Bit
2-0
Hardware registers can only be accessed through the parallel programming modes
which are handled by the parallel programmer.
Software registers are in a special page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called "Extra Flash Memory", is not in the internal Flash program memory
addressing space.
When this bit is programmed (‘1’ value) the boot address is 0000h.
When this bit is unprogrammed (‘1’ value) the boot address is F800h. By default,
this bit is unprogrammed and the ISP is enabled.
X2
7
6
5
4
3
7
Mnemonic
XRAM
LB2-0
BLJB
BLJB
Bit
X2
-
-
6
Description
X2 Mode
Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.
Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset
(Default).
Boot Loader Jump Bit
Unprogrammed (‘1’ value) to start the user’s application on next reset at address
0000h.
Programmed (‘0’ value) to start the boot loader at address F800h on next reset
(Default).
Reserved
Reserved
XRAM Config Bit (only programmable by programmer tools)
Programmed to inhibit XRAM after reset.
Unprogrammed, this bit to valid XRAM after reset (Default).
User Memory Lock Bits (only programmable by programmer tools)
See Table 66.
5
-
4
-
XRAM
3
AT89C51RB2/RC2
LB2
2
LB1
1
LB0
0
87