PIC18F2410-I/ML Microchip Technology, PIC18F2410-I/ML Datasheet - Page 177
![IC PIC MCU FLASH 8KX16 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F2410-I/ML
Manufacturer Part Number
PIC18F2410-I/ML
Description
IC PIC MCU FLASH 8KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18LF2410-ISO.pdf
(376 pages)
2.PIC18LF2410-ISO.pdf
(8 pages)
3.PIC18LF2410-ISO.pdf
(16 pages)
4.PIC18LF2410-ISO.pdf
(6 pages)
5.PIC18LF2410-ISO.pdf
(6 pages)
6.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18F2410-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2410-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18LF2410-ISO PDF datasheet
- PIC18LF2410-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18LF2410-ISO PDF datasheet #4
- PIC18LF2410-ISO PDF datasheet #5
- PIC18LF2410-ISO PDF datasheet #6
- Current page: 177 of 376
- Download datasheet (7Mb)
16.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 16-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
FIGURE 16-17:
TABLE 16-3:
© 2009 Microchip Technology Inc.
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
2
C interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE W/BRG
SSPM3:SSPM0
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C Master mode, the BRG is
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
F
CY
SCL
SSPM3:SSPM0
CY
) on the
Reload
Control
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CLKO
CY
* 2
Reload
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 16-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
2
BRG Down Counter
C specification (which applies to rates greater than
SSPADD<6:0>
PIC18F2X1X/4X1X
BRG Value
0Ch
18h
1Fh
63h
09h
27h
02h
09h
00h
F
OSC
/4
(2 Rollovers of BRG)
DS39636D-page 179
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)
(1)
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