PIC18F2410-I/ML Microchip Technology, PIC18F2410-I/ML Datasheet
PIC18F2410-I/ML
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PIC18F2410-I/ML Summary of contents
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... Dual Analog Comparators with Input Multiplexing • Programmable 16-Level High/Low-Voltage Detection (HLVD) module: - Supports interrupt on High/Low-Voltage Detection © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Flexible Oscillator Structure: • Four Crystal modes MHz • 4x Phase Lock Loop (PLL) – Available for Crystal and Internal Oscillators • ...
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... PIC18F2X1X/4X1X Data Program Memory Memory Device Flash # Single-Word SRAM (bytes) Instructions (bytes) PIC18F2410 16K 8192 PIC18F2510 32K 16384 1536 PIC18F2515 48K 24576 3968 PIC18F2610 64K 32768 3968 PIC18F4410 16K 8192 PIC18F4510 32K 16384 1536 PIC18F4515 48K 24576 3968 PIC18F4610 64K 32768 ...
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... RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 Note 1: RB3 is the alternate pin for CCP2 multiplexing. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X /RE3 REF + 5 REF ( -/ REF + 2 20 REF PIC18F2410 PIC18F2510 /RE3 REF REF ( RB7/KBI3/PGD RB6//KBI2/PGC ...
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... RB3 is the alternate pin for CCP2 multiplexing. DS39636D-page RC0/T1OSO/T13CKI 32 2 OSC2/CLKO/RA6 31 3 OSC1/CLKI/RA7 PIC18F4X1X RE2/CS/AN7 27 7 RE1/WR/AN6 26 8 RE0/RD/AN5 9 25 RA5/AN4/SS/HLVDIN/C2OUT 24 10 RA4/T0CKI/C1OUT 23 11 OSC2/CLKO/RA6 OSC1/CLKI/RA7 PIC18F4X1X RE2/CS/AN7 27 7 RE1/WR/AN6 8 26 RE0/RD/AN5 9 25 RA5/AN4/SS/HLVDIN/C2OUT 24 10 RA4/T0CKI/C1OUT 23 11 © 2009 Microchip Technology Inc. ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 363 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 363 Index ................................................................................................................................................................................................. 365 The Microchip Web Site ..................................................................................................................................................................... 375 Customer Change Notification Service .............................................................................................................................................. 375 Customer Support .............................................................................................................................................................................. 375 Reader Response .............................................................................................................................................................................. 376 PIC18F2X1X/4X1X Product Identification System............................................................................................................................. 377 © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X DS39636D-page 7 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39636D-page 8 © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F2410 • PIC18LF2410 • PIC18F2510 • PIC18LF2510 • PIC18F2515 • PIC18LF2515 • PIC18F2610 • PIC18LF2610 • PIC18F4410 • PIC18LF4410 • PIC18F4510 • PIC18LF4510 • PIC18F4515 • PIC18LF4515 • ...
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... Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash program memory • 16 Kbytes for PIC18F2410/4410 devices • 32 Kbytes for PIC18F2510/4510 devices • 48 Kbytes for PIC18F2515/4515 devices • 64 Kbytes for PIC18F2610/4610 devices 2. ...
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... TABLE 1-1: DEVICE FEATURES (PIC18F2410/2415/2510/2515/2610) Features PIC18F2410 Operating Frequency DC – 40 MHz Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Ports (E) Timers Capture/Compare/PWM Modules Enhanced Capture/Compare/PWM Modules Serial Communications Enhanced USART Parallel Communications (PSP) 10-bit Analog-to-Digital Module ...
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... Stack Underflow (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), WDT WDT Yes Yes Yes Yes 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended Instruction Set enabled 40-pin PDIP 40-pin PDIP 44-pin QFN 44-pin QFN 44-pin TQFP 44-pin TQFP © 2009 Microchip Technology Inc. ...
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... FIGURE 1-1: PIC18F2410/2415/2510/2515/2610 (28-PIN) BLOCK DIAGRAM Table Pointer<21> 8 inc/dec logic PCLATH PCLATU 21 20 PCU PCH PCL Program Counter 31 Level Stack Address Latch Program Memory STKPTR (16/32/48/64 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR State Machine Instruction Control Signals ...
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... RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT (3) OSC2/CLKO /RA6 (3) OSC1/CLKI /RA7 PORTB RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 (1) RB3/AN9/CCP2 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI (1) RC1/T1OSI/CCP2 RC2/CCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD0/PSP0 :RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D PORTE RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 (2) MCLR/V /RE3 PP © 2009 Microchip Technology Inc. ...
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... TABLE 1-3: PIC18F2410/2415/2510/2515/2610 PINOUT I/O DESCRIPTIONS Pin Number Pin Name SPDIP, QFN SOIC MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 9 6 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 7 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set ...
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... PIC18F2X1X/4X1X TABLE 1-3: PIC18F2410/2415/2510/2515/2610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, QFN SOIC RA0/AN0 2 27 RA0 AN0 RA1/AN1 3 28 RA1 AN1 RA2/AN2/V -/ REF REF RA2 AN2 V - REF CV REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI/C1OUT 6 3 RA4 T0CKI C1OUT RA5/AN4/SS/HLVDIN/ ...
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... TABLE 1-3: PIC18F2410/2415/2510/2515/2610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, QFN SOIC RB0/INT0/FLT0/AN12 21 18 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 22 19 RB1 INT1 AN10 RB2/INT2/AN8 23 20 RB2 INT2 AN8 RB3/AN9/CCP2 24 21 RB3 AN9 (1) CCP2 RB4/KBI0/AN11 25 22 RB4 KBI0 AN11 RB5/KBI1/PGM ...
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... PIC18F2X1X/4X1X TABLE 1-3: PIC18F2410/2415/2510/2515/2610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, QFN SOIC RC0/T1OSO/T13CKI 11 8 RC0 T1OSO T13CKI RC1/T1OSI/CCP2 12 9 RC1 T1OSI (2) CCP2 RC2/CCP1 13 10 RC2 CCP1 RC3/SCK/SCL 14 11 RC3 SCK SCL RC4/SDI/SDA 15 12 RC4 SDI SDA RC5/SDO 16 13 ...
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... ST = Schmitt Trigger input with CMOS levels Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Pin Buffer Type Type 18 Master Clear (input) or programming voltage (input). ...
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... I/O TTL Digital I/O. I Analog Analog input 4. I TTL SPI slave select input. I Analog High/Low-Voltage Detect input. O — Comparator 2 output. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. CMOS = CMOS compatible input or output = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... Digital I/O. O — EUSART asynchronous transmit. I/O ST EUSART synchronous clock (see related RX/DT). 1 I/O ST Digital I/ EUSART asynchronous receive. I/O ST EUSART synchronous data (see related TX/CK). CMOS = CMOS compatible input or output = Input P = Power Description 2 C™ mode. © 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Pin Buffer Type Type PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port ...
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... See MCLR — Ground reference for logic and I/O pins — Positive supply for logic and I/O pins. 12, 13, — — No connect. 33, 34 CMOS = CMOS compatible input or output = Input P = Power Description /RE3 pin. © 2009 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... FIGURE 2-4: Clock from Ext. System EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX RA6 I/O (OSC2) © 2009 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT C > EXT © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... Section 2.6.5.1 “Compensating with the USART”, Section 2.6.5.2 “Compensating with the Timers” and Section 2.6.5.3 “Compensating with the CCP Module in Capture Mode”, but other techniques may be used. or temperature changes, which can compensation techniques are © 2009 Microchip Technology Inc. ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X (1) U-0 R/W-0 ...
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... MHz 101 1 MHz 100 500 kHz 011 250 kHz FOSC3:FOSC0 010 125 kHz 001 31 kHz 1 000 0 OSCTUNE<7> © 2009 Microchip Technology Inc. Peripherals CPU IDLEN Clock Control OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Start-up ...
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... INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... Legend Readable bit -n = Value at POR DS39636D-page 32 (1) R/W-0 R/W-0 R R-0 IRCF1 IRCF0 OSTS IOFS (2) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X time clock. Other features may be operating that do not require a device clock source (i.e., SSP slave, PSP, INTn pins and others) ...
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... PIC18F2X1X/4X1X NOTES: DS39636D-page 34 © 2009 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. © 2009 Microchip Technology Inc. ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X n-1 ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC OST (1) (1) T PLL 1 2 n-1 n (2) Clock Transition PC OSTS bit set = 2 ms (approx). These intervals are not shown to scale. PLL . OSC © 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD © 2009 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...
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... OST EC CSD (2) INTOSC T IOBST is the PLL Lock-out Timer (parameter F12 (parameter 39), the INTOSC stabilization period. IOBST Clock Ready Status bit (OSCCON) OSTS (2) — IOFS (4) ( OSTS rc (2) (5) IOFS (5) (4) OSTS + t rc (2) IOFS (4) (4) OSTS + t rc (2) (5) IOFS © 2009 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. ...
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... POR was set to ‘1’ by software immediately after POR). DS39636D-page 44 (1) U-0 R/W-1 R-1 — (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared (2) R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X FIGURE 4- ...
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... BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. © 2009 Microchip Technology Inc. ...
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... INTIO1, INTIO2 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39636D-page PWRT T OST T PWRT T OST T PWRT T OST © 2009 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X , V RISE > PWRT T OST T PWRT T OST ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( STKPTR Register POR BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. WDT N/A N/A N/A N/A N/A ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. WDT (1) (1) (1) (5) (5) (5) ...
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... NOP instruction). The PIC18F2410/4410 and PIC18F2510 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. The PIC18F2510/4510 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Stack Pointer STKPTR<4:0> 00010 © 2009 Microchip Technology Inc. ...
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... Note 1: Bit 7 and bit 6 are cleared by user software POR. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads”. nn COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh © 2009 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2009 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... PIC18F2X1X/4X1X FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2410/4410 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...
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... FFh = 1100 00h Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
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... RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 7Fh 80h Access RAM High (SFRs) FFh © 2009 Microchip Technology Inc. ...
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... BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Data Memory 000h 0 ...
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... F91h — (2) F90h — (2) F8Fh — (2) F8Eh — (3) F8Dh LATE (3) F8Ch LATD F8Bh LATC F8Ah LATB F89h LATA (2) F88h — (2) F87h — (2) F86h — (2) F85h — (3) F84h PORTE (3) F83h PORTD F82h PORTC F81h PORTB F80h PORTA © 2009 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Bit 4 Bit 3 ...
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... CM1 CM0 0000 0111 53, 223 53, 129 xxxx xxxx 53, 129 xxxx xxxx TMR3CS TMR3ON 0000 0000 53, 127 . Reset values are shown for 40/44-pin devices; ‘ ’ See Section 2.6.4 “PLL in ‘ ’ This bit is © 2009 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Bit 4 Bit 3 ...
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... The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Purpose Register File” location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “ ...
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... FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g OV, etc.). ADDWF, INDF1, 1 FSR1H:FSR1L 000h Bank 0 100h Bank 1 200h Bank 2 300h Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2009 Microchip Technology Inc. ...
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... The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET ...
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... F00h Bank 15 F80h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F80h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. 00h 60h 80h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... Bank 0 addresses below 5Fh can still be addressed F80h by using the BSR. FFFh © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset Addressing mode. Operations that use the BSR (Access RAM bit is ‘ ...
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... PIC18F2X1X/4X1X NOTES: DS39636D-page 76 © 2009 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Table reads work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address ...
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... TABLAT. A typical method for reading data from program memory is shown in Example 6-1. Program Memory (Odd Byte Address) TBLPTR = xxxxx1 TBLRD TABLE POINTER OPERATIONS WITH TBLRD INSTRUCTIONS Operation on Table Pointer TBLPTR = xxxxx0 TABLAT Read Register © 2009 Microchip Technology Inc. ...
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... Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT Program Memory Table Latch Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X ; Load TBLPTR with the base ; address of the word ; read into TABLAT and increment ...
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... PIC18F2X1X/4X1X NOTES: DS39636D-page 80 © 2009 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X EXAMPLE 7- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ® ...
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... INT2IF INT2IE INT2IP IPEN IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEH/GIE GIEL/PEIE ...
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... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 84
... This feature allows for software polling. DS39636D-page 86 R/W-1 R/W-1 U-0 R/W-1 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 85
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X U-0 R/W-0 ...
Page 86
... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSPIF CCP1IF ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 87
... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X U-0 U-0 R/W-0 R/W-0 — — BCLIF ...
Page 88
... Legend Readable bit -n = Value at POR DS39636D-page 90 R/W-0 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE CCP1IE ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown ...
Page 89
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X U-0 U-0 R/W-0 R/W-0 — — BCLIE HLVDIE W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 90
... Legend Readable bit -n = Value at POR DS39636D-page 92 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP CCP1IP ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown ...
Page 91
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X U-0 U-0 R/W-1 R/W-1 — — BCLIP HLVDIP W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 92
... Section 4.1 “RCON Register”. (1) U-0 R/W-1 R-1 — ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared (1) R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 93
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 8.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
Page 94
... PIC18F2X1X/4X1X NOTES: DS39636D-page 96 © 2009 Microchip Technology Inc. ...
Page 95
... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. ...
Page 96
... System cycle clock output (F modes. O DIG LATA<7> data output. Disabled in External Oscillator modes. I TTL PORTA<7> data input. Disabled in External Oscillator modes. I ANA Main oscillator input connection. I ANA Main clock input connection. Description /4) in RC, INTIO1 and EC Oscillator OSC © 2009 Microchip Technology Inc. ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Bit 5 Bit 4 ...
Page 98
... PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB3 can be configured by the Configuration bit, CCP2MX, as the alternate peripheral pin for the CCP2 module (CCP2MX = 0). © 2009 Microchip Technology Inc. ...
Page 99
... PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X I/O I/O Type ...
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... Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF — TMR0IP — INT2IE INT1IE — VCFG1 VCFG0 PCFG3 PCFG2 Reset Bit 1 Bit 0 Values on page RB1 RB0 INT0IF RBIF 51 — RBIP 51 INT2IF INT1IF 51 PCFG1 PCFG0 53 © 2009 Microchip Technology Inc. ...
Page 101
... The user should refer to the corresponding peripheral section for additional information. Note Power-on Reset, these pins are configured as digital inputs. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins ...
Page 102
... LATC<7> data output PORTC<7> data input Asynchronous serial receive data input (USART module). O DIG Synchronous serial data output (USART module); takes priority over port data Synchronous serial data input (USART module). User must configure as an input. Description © 2009 Microchip Technology Inc. ...
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... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Control Register © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Reset ...
Page 104
... EXAMPLE 9-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2009 Microchip Technology Inc. ...
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... P1D 0 Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X I/O I/O Type O DIG LATD<0> data output. ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. DS39636D-page 108 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 IBOV PSPMODE — TRISE2 DC1B1 DC1B0 CCP1M3 CCP1M2 Reset Bit 1 Bit 0 Values on page RD1 RD0 TRISE1 TRISE0 54 CCP1M1 CCP1M0 53 © 2009 Microchip Technology Inc. ...
Page 107
... Register 9-1. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X The fourth pin of PORTE (MCLR/V /RE3 input PP only pin. Its operation is controlled by the MCLRE Con- figuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
Page 108
... R = Readable bit -n = Value at POR DS39636D-page 110 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 TRISE2 TRISE1 TRISE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X I/O I/O ...
Page 110
... PSPIF (PIR1<7>) Note: I/O pins have diode protection to V PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) One bit of PORTD D Q RDx pin CK TTL Data Latch PORTE Pins Read RD TTL Chip Select CS TTL Write WR TTL and © 2009 Microchip Technology Inc. ...
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... PSPIE ADIE (1) IPR1 PSPIP ADIP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Bit 5 ...
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... PIC18F2X1X/4X1X NOTES: DS39636D-page 114 © 2009 Microchip Technology Inc. ...
Page 113
... Prescale value Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-Bit mode is shown in Figure 10-1 ...
Page 114
... Sync with Internal Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0L TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 115
... RA6 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 10.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
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... PIC18F2X1X/4X1X NOTES: DS39636D-page 118 © 2009 Microchip Technology Inc. ...
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... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 118
... Special Event Trigger Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... C1 PIC18FXXXX 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq C1 ( kHz 27 pF Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 120
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. © 2009 Microchip Technology Inc. ...
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... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
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... PIC18F2X1X/4X1X NOTES: DS39636D-page 124 © 2009 Microchip Technology Inc. ...
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... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...
Page 124
... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 51 TMR2IF TMR1IF 54 TMR2IE TMR1IE 54 TMR2IP TMR1IP © 2009 Microchip Technology Inc. ...
Page 125
... Enables Timer3 0 = Stops Timer3 Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X A simplified block diagram of the Timer3 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The Timer3 module is controlled through the T3CON register (Register 13-1) ...
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... Clear TMR3 TMR3L 8 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR3H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 127
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 13.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 128
... PIC18F2X1X/4X1X NOTES: DS39636D-page 130 © 2009 Microchip Technology Inc. ...
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... Compare mode: trigger special event, reset timer, start A/D conversion on CCP2 match (CCPxIF bit is set) 11xx = PWM mode Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. two CCP Note: Throughout this section and Section 15 ...
Page 130
... Changing the pin assignment of CCP2 does not auto- matically change any requirements for configuring the port pin. Users must always verify that the appropriate TRIS register is configured correctly for CCP2 operation, regardless of where it is located. Interaction © 2009 Microchip Technology Inc. ...
Page 131
... CCP1CON<3:0> Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 14.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false inter- rupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
Page 132
... Reset) Set CCP1IF Output Compare Match Logic 4 CCP1CON<3:0> 0 Special Event Trigger 1 (Timer1/Timer3 Reset, A/D Trigger) T3CCP2 Set CCP2IF Compare Output Match Logic 4 CCP2CON<3:0> Event Trigger mode CCP1 pin TRIS Output Enable CCP2 pin TRIS Output Enable © 2009 Microchip Technology Inc. ...
Page 133
... These bits are unimplemented on 28-pin devices and read as ‘0’. 2: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Bit 5 Bit 4 ...
Page 134
... CCPR2H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. • OSC (TMR2 Prescale Value) L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2009 Microchip Technology Inc. ...
Page 135
... Section 15.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X EQUATION 14-3: PWM Resolution (max) Note: If the PWM duty cycle value is longer than the PWM period, the CCP2 pin will not be cleared ...
Page 136
... CCP2M2 PSSAC1 PSSAC0 PSSBD1 (1) (1) (1) PDC5 PDC4 PDC3 PDC2 Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 51 PD POR BOR 50 TMR2IF TMR1IF 54 TMR2IE TMR1IE 54 TMR2IP TMR1IP CCP1M1 CCP1M0 CCP2M1 CCP2M0 53 (1) (1) PSSBD0 53 (1) (1) (1) PDC1 PDC0 53 © 2009 Microchip Technology Inc. ...
Page 137
... ECCP module are the same as described for the standard CCP module. The control register for the Enhanced CCP module is shown in Register 15-1. It differs from the CCPxCON registers in PIC18F2410/2415/2510/2515/2610 devices in that the two Most Significant bits are implemented to control PWM functionality. R/W-0 R/W-0 R/W-0 ...
Page 138
... The latter is more generic and will work for either single or multi-output PWM. and Timer RC2 RD5 All 40/44-pin devices: CCP1 RD5/PSP5 P1A P1B P1A P1B and Section 14.3 “Compare for PWM Operation” or RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD7/PSP7 P1C P1D © 2009 Microchip Technology Inc. ...
Page 139
... CCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 15.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...
Page 140
... The general relationship of the outputs in all configurations is summarized in Figure 15-2. 9.77 kHz 39.06 kHz FFh FFh OSC log F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...
Page 141
... Prescale Value) OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCPDEL<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 15.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 0 Duty Cycle Period (1) (1) Delay Delay ...
Page 142
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ PIC18F4X1X FET Driver P1A FET Driver P1B V- V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period Period td (1) ( Load + V - FET Driver FET Driver © 2009 Microchip Technology Inc. ...
Page 143
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 144
... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD © 2009 Microchip Technology Inc. ...
Page 145
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X (1) Period , depending on the Timer2 prescaler value. The modulated P1B and P1D signals OSC Forward Period ...
Page 146
... OSC OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared the PSSAC1:PSSAC0 and R/W-0 R/W-0 R/W-0 (1) (1) (1) PDC2 PDC1 PDC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 147
... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Unimplemented on 28-pin devices and read as ‘0’. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X R/W-0 R/W-0 R/W-0 R/W-0 ( Writable bit U = Unimplemented bit, read as ‘ ...
Page 148
... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle ECCPASE Cleared by Firmware © 2009 Microchip Technology Inc. ...
Page 149
... Wait until TMRn overflows (TMRnIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCPAS<7>). © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 15.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
Page 150
... Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 51 PD POR BOR 50 TMR2IF TMR1IF 54 TMR2IE TMR1IE 54 TMR2IP TMR1IP 54 TMR3IF CCP2IF 54 TMR3IE CCP2IE 54 TMR3IP CCP2IP TMR1CS TMR1ON TMR3CS TMR3ON CCP1M1 CCP1M0 53 (1) (1) PSSBD1 PSSBD0 53 (1) (1) (1) PDC2 PDC1 PDC0 53 © 2009 Microchip Technology Inc. ...
Page 151
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 16.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four SPI modes are supported ...
Page 152
... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 ...
Page 154
... Example 16-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. © 2009 Microchip Technology Inc. ...
Page 155
... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 16.3.4 TYPICAL CONNECTION Figure 16-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 156
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...
Page 157
... SSPIF Interrupt Flag SSPSR to SSPBUF © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application ...
Page 158
... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39636D-page 160 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 2 bit 5 bit 4 bit bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...
Page 159
... These bits are unimplemented on 28-pin devices and read as ‘0’. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 16.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
Page 160
... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When the © 2009 Microchip Technology Inc. ...
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... SSPBUF is empty In Receive mode SSPBUF is full (does not include the ACK and Stop bits SSPBUF is empty (does not include the ACK and Stop bits) Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 2 C MODE) R-0 R-0 R-0 D/A ...
Page 162
... SSPEN CKP SSPM3 SSPM2 2 /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C conditions were not valid for Bit is unknown © 2009 Microchip Technology Inc. ...
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... Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 2 C MODE) R/W-0 R/W-0 ...
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... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. © 2009 Microchip Technology Inc. ...
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... The clock must be released by setting bit CKP (SSPCON<4>). See Section 16.4.4 “Clock Stretching” for more detail. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 16.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F2X1X/4X1X 2 FIGURE 16-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39636D-page 168 © 2009 Microchip Technology Inc. ...
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... FIGURE 16-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X DS39636D-page 169 ...
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... PIC18F2X1X/4X1X 2 FIGURE 16-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39636D-page 170 © 2009 Microchip Technology Inc. ...
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... FIGURE 16-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X DS39636D-page 171 ...
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... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 16-11). © 2009 Microchip Technology Inc. ...
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... SDA DX SCL CKP WR SSPCON © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 16-12) ...
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... PIC18F2X1X/4X1X 2 FIGURE 16-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39636D-page 174 © 2009 Microchip Technology Inc. ...
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... FIGURE 16-14: I C™ SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X DS39636D-page 175 ...
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... Acknowledge (Figure 16-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’ © 2009 Microchip Technology Inc. ...
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... Generate a Stop condition on SDA and SCL. FIGURE 16-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...
Page 176
... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. © 2009 Microchip Technology Inc. ...
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... The I C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
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... DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count 03h 02h © 2009 Microchip Technology Inc. ...
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... FIGURE 16-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the ...
Page 180
... SSPCON2 is disabled until the Repeated Start condition is complete. S bit set by hardware SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated Start 1st bit T BRG © 2009 Microchip Technology Inc. ...
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... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 16.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
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... PIC18F2X1X/4X1X 2 FIGURE 16-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39636D-page 184 © 2009 Microchip Technology Inc. ...
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... FIGURE 16-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X DS39636D-page 185 ...
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... PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition WCOL Status Flag ACKEN automatically cleared Cleared in software BRG © 2009 Microchip Technology Inc. ...
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... FIGURE 16-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X 16.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...
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... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. SSP module reset into Idle state. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software © 2009 Microchip Technology Inc. ...
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... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 ...
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... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG © 2009 Microchip Technology Inc. ‘0’ ‘0’ Interrupt cleared in software ‘0’ ...
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... SCL PEN BCLIF P SSPIF © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> ...
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... PIC18F2X1X/4X1X NOTES: DS39636D-page 192 © 2009 Microchip Technology Inc. ...
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... Synchronous – Master (half duplex) with selectable clock polarity • Synchronous – Slave (half duplex) with selectable clock polarity © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX/ USART: • ...
Page 192
... R = Readable bit -n = Value at POR DS39636D-page 194 R/W-0 R/W-0 R/W-0 TX9 TXEN SYNC SENDB W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X R/W-0 R/W-0 R/W-0 RX9 SREN CREN ...
Page 194
... R = Readable bit -n = Value at POR DS39636D-page 196 R-1 U-0 R/W-0 R/W-0 — SCKP BRG16 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 R/W-0 R/W-0 — WUE ABDEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SPBRG EUSART Baud Rate Generator Register, Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency ...
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... SPBRG Actual SPBRG % value Rate value Error (K) (decimal) (decimal) — — — — — — — — 255 2403 -0.16 207 64 9615 -0. 19230 -0. 55555 3. — — — SPBRG value (decimal) 207 51 25 — — — — © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F2X1X/4X1X SYNC = 0, BRGH = 0, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (K) (decimal) ...
Page 198
... EUSART transmitter cannot be used during ABD. This means that whenever the ABDEN bit is set, TXREG cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSART operation. © 2009 Microchip Technology Inc. /32 ...
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... Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. FIGURE 17-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RX pin ABDOVF bit BRG Value XXXXh © 2009 Microchip Technology Inc. PIC18F2X1X/4X1X Edge #2 Edge #3 Edge #1 Bit 1 Bit 3 Start Bit 0 ...
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... If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Data Bus TXREG Register 8 MSb LSb (8) • • • 0 TSR Register TRMT TX9 TX9D ), the TXREG register is empty CY Pin Buffer and Control TX pin SPEN © 2009 Microchip Technology Inc. ...