DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 5

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

4. Module: Early Termination of Nested DO
EXAMPLE 4:
EXAMPLE 5:
EXAMPLE 6:
EXAMPLE 7:
© 2008 Microchip Technology Inc.
LOOP1: MOV
LOOP0: MOV
Note:
.include
...
DISI
BCLR
...
.include “p30fxxxx.h”
...
__asm__ volatile (“DISI #0x1FFF”);// protect CPU IPL modification
SRbits.IPL = 0x5;
DISICNT = 0x0;
#define DISI_PROTECT(X) { \
DISI_PROTECT(SRbits.IPL = 0x5);
...
When using two DO loops in a nested fashion,
terminating the inner-level DO loop by setting the
EDT (CORCON<11>) bit will produce unexpected
results. Specifically, the device may continue
executing code within the outer DO loop forever.
This erratum does not affect the operation of the
MPLAB C30 compiler.
Work around
The application should save the DCOUNT SFR
prior to entering the inner DO loop and restore it
upon exiting the inner DO loop. This work around is
shown in Example 4.
__asm__ volatile (“DISI #0x1FFF”);\
X;
DISICNT = 0; }
.include “p30fxxxx.inc”
.......
DO
....
PUSH COUNT
DO
BTSS Flag, #0
BSET CORCON, #EDT ;Terminate inner
....
....
POP
For details on the functionality of
EDT bit, see section 2.9.2.4 in the
dsPIC30F Family Reference Manual.
....
#2
IEC1, #INT1IE
Loops
#CNT1, LOOP0 ;Outer loop start
#CNT2, LOOP1 ;Inner loop
W1, W5
DCOUNT
W5, W8
SAVE AND RESTORE
DCOUNT
USING DISI
RAISING CPU INTERRUPT PRIORITY LEVEL
USING MACRO
“p30fxxxx.inc”
// set CPU IPL to 5
// remove DISI protection
;Save DCOUNT
;starts
;DO-loop early
;Inner loop ends
;Restore DCOUNT
;Outer loop ends
\
; protect the disable of INT1
; disable interrupt 1
; next instruction protected by DISI
// safely modify the CPU IPL
5. Module: Interrupt Controller – Sequential
dsPIC30F3012/3013
When interrupt nesting is enabled (or NSTDIS
(INTCON1<15>) bit is ‘0’), the following sequence
of events will lead to an address error trap. The
generic terms “Interrupt 1” and “Interrupt 2” are
used to represent any two enabled dsPIC30F
interrupts.
1. Interrupt 1 processing begins.
2. Interrupt 1 is negated by user software by one
3. Interrupt 2 occurs with a priority higher than
Work around
The user may disable interrupt nesting or execute
a DISI instruction before modifying the CPU IPL
or Interrupt 1 setting. A minimum DISI value of 2
is required if the DISI is executed immediately
before the CPU IPL or Interrupt 1 is modified, as
shown in Example 5. If the MPLAB C30 compiler
is being used, one must inspect the Disassembly
Listing in the MPLAB IDE file to determine the
exact number of cycles to disable level 1-6
interrupts. One may use a large DISI value and
then set the DISICNT register to zero, as shown in
Example 6. A macro may also be used to perform
this task, as shown in Example 7.
of the following methods:
- CPU IPL is raised to Interrupt 1 IPL level or
- Interrupt 1 IPL is lowered to CPU IPL level or
- Interrupt 1 is disabled (Interrupt 1 IE bit set to
- Interrupt 1 flag is cleared
Interrupt 1.
higher or
lower or
‘0’) or
Interrupts
DS80255F-page 5