PIC18F6390-I/PT Microchip Technology, PIC18F6390-I/PT Datasheet
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... PIC18F6390/6490/8390/8490 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology 2004 Microchip Technology Inc. Data Sheet Preliminary DS39629B ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F8490 16K 8192 768 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Peripheral Highlights: • High current sink/source 25 mA/25 mA • Four external interrupts • Four input-change interrupts • Four 8-bit/16-bit Timer/Counter modules • Real-Time Clock (RTC) Software module: - Configurable 24-hour clock, calendar, automatic ...
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... RG1/TX2/CK2/SEG29 4 RG2/RX2/DT2/SEG28 5 RG3/SEG27 6 MCLR/V /RG5 PP 7 RG4/SEG26 RF7/SS/SEG25 11 RF6/AN11/SEG24 12 RF5/AN10/CV /SEG23 REF 13 RF4/AN9/SEG22 14 RF3/AN8/SEG21 15 RF2/AN7/C1OUT/SEG20 16 Note 1: RE7 is the alternate pin for CCP2 multiplexing DS39629B-page PIC18F6390 PIC18F6490 Preliminary 50 49 RB0/INT0 48 RB1/INT1/SEG8 47 RB2/INT2/SEG9 46 RB3/INT3/SEG10 45 RB4/KBI0/SEG11 44 RB5/KBI1 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI/RA7 RB7/KBI3/PGD 37 RC5/SDO/SEG12 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 ...
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... MCLR/V /RG5 PP 9 RG4/SEG26 RF7/SS/SEG25 13 RF6/AN11/SEG24 14 RF5/AN10/CV /SEG23 REF 15 RF4/AN9/SEG22 16 RF3/AN8/SEG21 17 RF2/AN7/C1OUT/SEG20 18 RH7/SEG43 19 RH6/SEG42 Note 1: RE7 is the alternate pin for CCP2 multiplexing 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 PIC18F8390 PIC18F8490 Preliminary RJ2/SEG34 60 RJ3/SEG35 59 RB0/INT0 58 RB1/INT1/SEG8 57 RB2/INT2/SEG9 56 RB3/INT3/SEG10 55 RB4/KBI0/SEG11 54 RB5/KBI1 53 RB6/KBI2/PGC OSC2/CLKO/RA6 ...
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... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 395 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 395 Index .................................................................................................................................................................................................. 397 On-Line Support................................................................................................................................................................................. 407 Systems Information and Upgrade Hot Line ...................................................................................................................................... 407 Reader Response .............................................................................................................................................................................. 408 PIC18F6390/6490/8390/8490 Product Identification System ............................................................................................................ 409 DS39629B-page 4 Preliminary 2004 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Preliminary DS39629B-page 5 ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629B-page 6 Preliminary 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F6390/6490/8390/8490 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F6390/6490/8390/8490 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators. ...
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... Like all Microchip PIC18 devices, members of the PIC18F6390/6490/8390/8490 family are available as both standard and low-voltage devices. Standard devices with Flash memory, designated with an “F” in the part number (such as PIC18F6390), accommodate an operating V range of 4.2V to 5.5V. Low-voltage DD parts, designated by “LF” (such as PIC18LF6490), ...
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... Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) POR, BOR, RESET Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Packages 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 PIC18F6390 PIC18F6490 DC – 40 MHz DC – 40 MHz 8K 16K 4096 8192 768 768 ...
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... PIC18F6390/6490/8390/8490 FIGURE 1-1: PIC18F6X90 (64-PIN) BLOCK DIAGRAM Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH Program Counter 31 Level Stack Address Latch Program Memory STKPTR (48/64 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction Decode and Control Internal ...
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... RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Data Bus<8> Data Latch 8 8 Data Memory (3 ...
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... PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP MCLR/V /RG5 7 PP MCLR V PP RG5 OSC1/CLKI/RA7 39 OSC1 CLKI RA7 OSC2/CLKO/RA6 40 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O. I Analog Analog input 0 ...
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... PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0 48 RB0 INT0 RB1/INT1/SEG8 47 RB1 INT1 SEG8 RB2/INT2/SEG9 46 RB2 INT2 SEG9 RB3/INT3/SEG10 45 RB3 INT3 SEG10 RB4/KBI0/SEG11 44 RB4 KBI0 SEG11 RB5/KBI1 43 RB5 KBI1 RB6/KBI2/PGC 42 RB6 KBI2 PGC RB7/KBI3/PGD 37 RB7 ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. O — ...
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... PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/SEG0 58 RD0 SEG0 RD1/SEG1 55 RD1 SEG1 RD2/SEG2 54 RD2 SEG2 RD3/SEG3 53 RD3 SEG3 RD4/SEG4 52 RD4 SEG4 RD5/SEG5 51 RD5 SEG5 RD6/SEG6 50 RD6 SEG6 RD7/SEG7 49 RD7 SEG7 Legend: TTL = TTL compatible input ...
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... Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTE is a bidirectional I/O port. I Analog BIAS1 input for LCD. ...
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... PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF0/AN5/SEG18 18 RF0 AN5 SEG18 RF1/AN6/C2OUT/SEG19 17 RF1 AN6 C2OUT SEG19 RF2/AN7/C1OUT/SEG20 16 RF2 AN7 C1OUT SEG20 RF3/AN8/SEG21 15 RF3 AN8 SEG21 RF4/AN9/SEG22 14 RF4 AN9 SEG22 RF5/AN10/CV /SEG23 13 REF RF5 AN10 CV REF ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O. O Analog SEG30 output for LCD ...
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... PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP MCLR/V /RG5 9 PP MCLR V PP RG5 OSC1/CLKI/RA7 49 OSC1 CLKI RA7 OSC2/CLKO/RA6 50 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O. I Analog Analog input 0 ...
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... PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0 58 RB0 INT0 RB1/INT1/SEG8 57 RB1 INT1 SEG8 RB2/INT2/SEG9 56 RB2 INT2 SEG9 RB3/INT3/SEG10 55 RB3 INT3 SEG10 RB4/KBI0/SEG11 54 RB4 KBI0 SEG11 RB5/KBI1 53 RB5 KBI1 RB6/KBI2/PGC 52 RB6 KBI2 PGC RB7/KBI3/PGD 47 RB7 ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. O — ...
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... PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/SEG0 72 RD0 SEG0 RD1/SEG1 69 RD1 SEG1 RD2/SEG2 68 RD2 SEG2 RD3/SEG3 67 RD3 SEG3 RD4/SEG4 66 RD4 SEG4 RD5/SEG5 65 RD5 SEG5 RD6/SEG6 64 RD6 SEG6 RD7/SEG7 63 RD7 SEG7 Legend: TTL = TTL compatible input ...
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... Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTE is a bidirectional I/O port. I Analog BIAS1 input for LCD. ...
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... PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF0/AN5/SEG18 24 RF0 AN5 SEG18 RF1/AN6/C2OUT/SEG19 23 RF1 AN6 C2OUT SEG19 RF2/AN7/C1OUT/SEG20 18 RF2 AN7 C1OUT SEG20 RF3/AN8/SEG21 17 RF3 AN8 SEG21 RF4/AN9/SEG22 16 RF4 AN9 SEG22 RF5/AN10/CV /SEG23 15 REF RF5 AN10 CV REF ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O. O Analog SEG30 output for LCD ...
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... PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RH0/SEG47 79 RH0 SEG47 RH1/SEG46 80 RH1 SEG46 RH2/SEG45 1 RH2 SEG45 RH3/SEG44 2 RH3 SEG44 RH4/SEG40 22 RH4 SEG40 RH5/SEG41 21 RH5 SEG41 RH6/SEG42 20 RH6 SEG42 RH7/SEG43 19 RH7 SEG43 Legend: TTL = TTL compatible input ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTJ is a bidirectional I/O port. I/O ST Digital I/O. O Analog SEG32 output for LCD ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629B-page 30 Preliminary 2004 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types PIC18F6390/6490/8390/8490 devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL enabled 5 ...
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... PIC18F6390/6490/8390/8490 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz 33 pF 200 kHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... EXT C > EXT 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit clock the device up to its highest rated frequency from a crystal oscillator. This may be ...
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... PIC18F6390/6490/8390/8490 2.6 Internal Oscillator Block The PIC18F6390/6490/8390/8490 devices include an internal oscillator block, which generates two different clock signals; either can be used as the micro- controller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. ...
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... Minimum frequency Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2.6.5.3 Compensating with the Timers A CCP module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F6390/6490/8390/8490 devices are shown in Figure 2-8. See Section 23.0 “Special Features of the CPU” for configuration register details ...
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... Timer1 oscillator starts. 2.7.2 OSCILLATOR TRANSITIONS PIC18F6390/6490/8390/8490 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F6390/6490/8390/8490 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 IDLEN IRCF2 bit 7 bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (INTOSC drives clock directly) ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 2.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629B-page 40 Preliminary 2004 Microchip Technology Inc. ...
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... POWER MANAGED MODES PIC18F6390/6490/8390/8490 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power managed modes: • Sleep mode • ...
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... PIC18F6390/6490/8390/8490 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 T1OSI OSC1 T PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits changed Note 1024 OST OSC PLL 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 n-1 n Clock Transition (1) (1) OST T PLL 1 2 n-1 ...
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... PIC18F6390/6490/8390/8490 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code ...
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... The Power Managed Sleep mode PIC18F6390/6490/8390/8490 devices is identical to the Legacy Sleep mode offered in all other PICmicro devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (see Figure 3-5). All clock source status bits are cleared ...
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... PIC18F6390/6490/8390/8490 3.4.1 PRI_IDLE MODE This mode is unique among the three Low-Power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... In such situations, initial oscillator operation is far from stable and unpredictable operation may result. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the periph- erals continue to be clocked from the internal oscillator block using the INTOSC multiplexer ...
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... PIC18F6390/6490/8390/8490 3.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power managed modes. The clocking subsystem actions are discussed in each of the power managed modes (see Section 3.2 “ ...
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... Includes both the INTOSC 8 MHz source and postscaler derived frequencies the Oscillator Start-up Timer (parameter 32). t OST also designated PLL 5: Execution continues during T 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Clock Source Exit Delay after Wake-up LP, XT, HS HSPLL T CSD (1) EC, RC, INTRC (3) INTOSC ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629B-page 50 Preliminary 2004 Microchip Technology Inc. ...
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... RESET The PIC18F6390/6490/8390/8490 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F6390/6490/8390/8490 REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 IPEN SBOREN bit 7 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit If BOREN1:BOREN0 = 01 BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00 11: Bit is disabled and read as ‘ ...
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... The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F6390/6490/8390/8490 devices, the MCLR input can be disabled with the MCLRE configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 9.7 “PORTG, TRISG and LATG Registers” ...
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... PIC18F6390/6490/8390/8490 4.4 Brown-out Reset (BOR) PIC18F6390/6490/8390/8490 devices implement a BOR circuit that provides the user with a number of configuration and power saving options. The BOR is controlled by the BORV1:BORV0 BOREN1:BOREN0 configuration bits. There are a total of four BOR configurations, which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any values of BOREN1:BOREN0 except ‘ ...
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... POWER-UP TIMER (PWRT) The Power-up Timer PIC18F6390/6490/8390/8490 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 µs = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation ...
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... PIC18F6390/6490/8390/8490 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 , V RISE > PWRT T OST T PWRT T OST T ...
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... PIC18F6390/6490/8390/8490 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F6390/6490/8390/8490 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices FSR1H 6X90 8X90 FSR1L 6X90 8X90 BSR 6X90 8X90 INDF2 6X90 8X90 POSTINC2 6X90 8X90 POSTDEC2 6X90 8X90 PREINC2 6X90 8X90 PLUSW2 6X90 8X90 FSR2H 6X90 8X90 FSR2L 6X90 8X90 ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F6390/6490/8390/8490 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices TRISJ 6X90 8X90 TRISH 6X90 8X90 TRISG 6X90 8X90 TRISF 6X90 8X90 TRISE 6X90 8X90 TRISD 6X90 8X90 TRISC 6X90 8X90 TRISB 6X90 8X90 (5) TRISA 6X90 8X90 LATJ 6X90 8X90 ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F6390/6490/8390/8490 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices LCDSE5 6X90 8X90 LCDSE4 6X90 8X90 LCDSE3 6X90 8X90 LCDSE2 6X90 8X90 LCDSE1 6X90 8X90 LCDSE0 6X90 8X90 LCDCON 6X90 8X90 LCDPS 6X90 8X90 Legend unchanged unknown unimplemented bit, read as ‘0’ value depends on condition. ...
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... Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F6390/6490/8390/8490 DEVICES PIC18F6390/8390 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 • ...
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... PIC18F6390/6490/8390/8490 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software, or until a POR occurs ...
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... PIC18F6390/6490/8390/8490 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... PIC18F6390/6490/8390/8490 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘ ...
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... PIC18F6390/6490/8390/8490 devices only 4 banks. Figure 5-5 shows the data memory organization for the PIC18F6390/6490/8390/8490 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’ ...
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... PIC18F6390/6490/8390/8490 FIGURE 5-5: DATA MEMORY MAP FOR PIC18F6390/6490/8390/8490 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh = 0011 Bank 1110 Bank 14 00h = 1111 Bank 15 FFh DS39629B-page 72 Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh ...
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... BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Data Memory 000h 7 00h Bank 0 ...
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... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy three-quarters of Bank 15 (from F40h to FFFh). A list of these registers is given in Table 5-1 and Table 5-2. TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F6390/6490/8390/8490 DEVICES Address Name Address FFFh ...
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... TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F6390/6490/8390/8490 DEVICES (CONTINUED) Address Name Address F7Fh SPBRGH1 F7Eh BAUDCON1 (2) F7Dh — (4) F7Ch LCDDATA23 (4) F7Bh LCDDATA22 F7Ah LCDDATA21 F79h LCDDATA20 F78h LCDDATA19 F77h LCDDATA18 (4) F76h LCDDATA17 (4) F75h LCDDATA16 F74h LCDDATA15 F73h LCDDATA14 F72h LCDDATA13 ...
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... PIC18F6390/6490/8390/8490 TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY File Name Bit 7 Bit 6 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF PCLATU — — PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN IRCF2 IRCF1 HLVDCON VDIRMAG — IRVST WDTCON — — (1) RCON IPEN SBOREN TMR1H Timer1 Register High Byte ...
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... PIC18F6390/6490/8390/8490 TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 SPBRG1 EUSART1 Baud Rate Generator RCREG1 EUSART1 Receive Register TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN RCSTA1 SPEN RX9 SREN IPR3 — LCDIP RC2IP PIR3 — LCDIF RC2IF PIE3 — ...
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... TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 SPBRGH1 EUSART1 Baud Rate Generator High Byte BAUDCON1 ABDOVF RCIDL (6) LCDDATA23 S47C3 S46C3 S45C3 (6) LCDDATA22 S39C3 S38C3 S37C3 LCDDATA21 S31C3 S30C3 S29C3 LCDDATA20 S23C3 S22C3 S21C3 LCDDATA19 S15C3 S14C3 S13C3 ...
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... PIC18F6390/6490/8390/8490 5.3.5 STATUS REGISTER The Status register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the Status register is the destination for an instruction that affects the Z, DC bits, the results of the instruction are not written ...
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... Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 “General 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Purpose Register File”), or a location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. ...
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... PIC18F6390/6490/8390/8490 5.4.3.1 FSR Registers and the INDF Operand At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
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... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 5.4.3.3 Operations by FSRs on FSRs Indirect addressing operations that target other FSRs or virtual registers represent special cases. For exam- ple, using an FSR to point to one of the virtual registers will not result in successful operations ...
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... PIC18F6390/6490/8390/8490 5.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds five addi- tional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 5.2.4 “ ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 000h 060h Bank 0 100h Bank 1 through Bank 14 F00h ...
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... PIC18F6390/6490/8390/8490 5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user defined “ ...
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... FLASH PROGRAM MEMORY In PIC18F6390/6490/8390/8490 devices, the program memory is implemented as read-only Flash memory readable over the entire V range during normal DD operation. A read from program memory is executed on one byte at a time. 6.1 Table Reads For PIC18 devices, there are two operations that allow ...
Page 90
... PIC18F6390/6490/8390/8490 6.2 Control Registers Two control registers are used in conjunction with the TBLRD instruction: the TABLAT register and the TBLPTR register set. 6.2.1 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM ...
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... Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT Program Memory Table Latch Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 ; Load TBLPTR with the base ; address of the word ; read into TABLAT and increment ; get data ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629B-page 90 Preliminary 2004 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 EXAMPLE 7-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 7-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
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... PIC18F6390/6490/8390/8490 Example 7-3 shows the sequence unsigned multiplication. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 7- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = (ARG1H • ARG2H • (ARG1H • ARG2L • 2 (ARG1L • ARG2H • 2 (ARG1L • ...
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... INTERRUPTS The PIC18F6390/6490/8390/8490 devices have multi- ple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress ...
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... PIC18F6390/6490/8390/8490 FIGURE 8-1: PIC18F6X90/8X90 INTERRUPT LOGIC PIR1<6:0> PIE1<6:0> IPR1<6:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> PIR3<6:4> PIE3<6:4> IPR3<6:4> High Priority Interrupt Generation Low Priority Interrupt Generation PIR1<6:0> PIE1<6:0> IPR1<6:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> PIR3<6:4> PIE3<6:4> IPR3<6:4> DS39629B-page 94 TMR0IF TMR0IE ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt ...
Page 98
... PIC18F6390/6490/8390/8490 REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge ...
Page 99
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an inter- rupt. This feature allows for software polling. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 R/W-0 R/W-0 R/W-0 INT3IE ...
Page 100
... PIC18F6390/6490/8390/8490 8.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 101
... A TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 U-0 U-0 R/W-0 — — BCLIF W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 102
... PIC18F6390/6490/8390/8490 REGISTER 8-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 R/W-0 — LCDIF bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIF: LCD Interrupt Flag bit (Valid when Type-B waveform with Non-Static mode is selected LCD data of all COMs is output (must be cleared in software) ...
Page 103
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 R/W-0 R/W-0 R/W-0 ADIE RC1IE TX1IE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...
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... PIC18F6390/6490/8390/8490 REGISTER 8-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 OSCFIE CMIE bit 7 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCLIE: Bus Collision Interrupt Enable bit ...
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... TX2IE: AUSART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 R-0 R-0 U-0 RC2IE TX2IE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
Page 106
... PIC18F6390/6490/8390/8490 8.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 107
... High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 U-0 U-0 R/W-1 — — BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
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... PIC18F6390/6490/8390/8490 REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 R/W-0 — LCDIP bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIP: LCD Interrupt Priority bit (valid when Type-B waveform with Non-Static mode is selected High priority 0 = Low priority bit 5 RC2IP: AUSART Receive Priority Flag bit ...
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... For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 U-0 R/W-1 R-1 — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 110
... PIC18F6390/6490/8390/8490 8.6 INTn Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxF is set ...
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... PORTA pin an output (i.e., put the contents of the output latch on the selected pin). 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. The Data Latch register (LATA) is also memory mapped ...
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... PIC18F6390/6490/8390/8490 TABLE 9-1: PORTA FUNCTIONS TRIS Pin Name Function Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/V -/S RA2 REF 0 EG16 1 AN2 REF 1 SEG16 x RA3/AN3/V +/ RA3 0 REF SEG17 1 AN3 REF 1 SEG17 x RA4/T0CKI/ RA4 0 SEG14 1 T0CKI SEG14 x RA5/AN4/ RA5 0 HLVDIN/SEG15 1 AN4 ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F6390/6490/8390/8490 9.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
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... PWR = Power Supply Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: All other pin functions are disabled when ICSP or ICD are enabled. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 I/O Buffer O DIG LATB< ...
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... PIC18F6390/6490/8390/8490 TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB Data Output Register TRISB PORTB Data Direction Register INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP LCDSE1 SE15 SE14 Legend: Shaded cells are not used by PORTB ...
Page 117
... TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Note Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides ...
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... PIC18F6390/6490/8390/8490 TABLE 9-5: PORTC FUNCTIONS TRIS Pin Name Function Setting RC0/T1OSO/ RC0 0 T13CKI/ 1 T1OSO x T13CKI x RC1/T1OSI/ RC1 0 CCP2 1 T1OSI x (1) CCP2 0 1 RC2/CCP1/ RC2 0 SEG13 1 CCP1 0 1 SEG13 x RC3/SCK/SCL RC3 0 1 SCK 0 1 SCL 0 1 RC4/SDI/SDA RC4 0 1 SDI 1 SDA 1 1 RC5/SDO/ ...
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... PORTC RC7 RC6 LATC LATC Data Output Register TRISC PORTC Data Direction Register LCDSE1 SE15 SE14 Legend: Shaded cells are not used by PORTC. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 SE13 SE12 SE11 SE10 ...
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... PIC18F6390/6490/8390/8490 9.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
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... SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 PORTD RD7 RD6 LATD LATD Data Output Register TRISD PORTD Data Direction Register LCDSE0 SE7 SE6 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 SE5 SE4 SE3 SE2 Preliminary Reset ...
Page 122
... PIC18F6390/6490/8390/8490 9.5 PORTE, TRISE and LATE Registers PORTE is a 4-bit wide, bidirectional port. The corre- sponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i ...
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... LCDEN SLPEN LCDSE3 SE31 SE30 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Buffer DIG LATE<4> data output; disabled when LCD common enabled. ST PORTE<4> data input. ANA Common 1 analog output for LCD. ...
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... PIC18F6390/6490/8390/8490 9.6 PORTF, LATF and TRISF Registers PORTF is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i ...
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... PWR = Power Supply Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 I/O Buffer ...
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... PIC18F6390/6490/8390/8490 TABLE 9-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name Bit 7 Bit 6 TRISF PORTF Data Direction Control Register PORTF Read PORTF pin/Write PORTF Data Latch LATF Read PORTF Data Latch/Write PORTF Data Latch ADCON1 — — CMCON C2OUT C1OUT CVRCON CVREN CVROE ...
Page 127
... TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 PORTG<4:0> are also multiplexed with LCD segment drives controlled by bits in the LCDSE3 register. I/O port functions are only available when the segments are disabled ...
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... PIC18F6390/6490/8390/8490 TABLE 9-14: PORTG FUNCTIONS TRIS Pin Name Function Setting RG0/SEG30 RG0 0 1 SEG30 x RG1/TX2/CK2/ RG1 0 SEG29 1 TX2 1 CK2 1 1 SEG29 x RG2/RX2/DT2/ RG2 0 SEG28 1 RX2 1 DT2 1 1 SEG28 x RG3/SEG27 RG3 0 1 SEG27 0 RG4/SEG26 RG4 0 1 SEG26 x (1) MCLR/V /RG5 MCLR — ...
Page 129
... On a Power-on Reset, these pins are configured as digital inputs. PORTH is also multiplexed with LCD segment drives controlled by the LCDSE5 register. I/O port functions are only available when the segments are disabled. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 EXAMPLE 9-8: CLRF PORTH CLRF LATH ...
Page 130
... PIC18F6390/6490/8390/8490 TABLE 9-16: PORTH FUNCTIONS TRIS Pin Name Function Setting RH0/SEG47 RH0 0 1 SEG47 x RH1/SEG46 RH1 0 1 SEG46 x RH2/SEG45 RH2 0 1 SEG45 x RH3/SEG44 RH3 0 1 SEG44 x RH4/SEG40 RH4 0 1 SEG40 x RH5/SEG41 RH5 0 1 SEG41 x RH6/SEG42 RH6 0 1 SEG42 x RH7/SEG43 RH7 0 1 SEG43 ...
Page 131
... On a Power-on Reset, these pins are configured as digital inputs. PORTJ is also multiplexed with LCD segment drives controlled by the LCDSE4 register. I/O port functions are only available when the segments are disabled. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 EXAMPLE 9-9: CLRF PORTJ ; Initialize PORTG by ; clearing output ...
Page 132
... PIC18F6390/6490/8390/8490 TABLE 9-18: PORTJ FUNCTIONS TRIS Pin Name Function Setting RJ0/SEG32 RJ0 0 1 SEG32 x RJ1/SEG33 RJ1 0 1 SEG33 x RJ2/SEG34 RJ2 0 1 SEG34 x RJ3/SEG35 RJ3 0 1 SEG35 x RJ4/SEG39 RJ4 0 1 SEG39 x RJ5/SEG38 RJ5 0 1 SEG38 x RJ6/SEG37 RJ6 0 1 SEG37 x RJ7/SEG36 RJ7 0 1 SEG36 ...
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... Prescale value Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 10-1. Figure 10-2 shows a simplified block diagram of the Timer0 module in 16-bit mode ...
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... PIC18F6390/6490/8390/8490 10.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default, unless a different prescaler value is selected (see Section 10.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... T0CON TMR0ON T08BIT TRISA PORTA Data Direction Register Legend: Shaded cells are not used by Timer0. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 10.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. the prescaler 10 ...
Page 136
... PIC18F6390/6490/8390/8490 NOTES: DS39629B-page 134 Preliminary 2004 Microchip Technology Inc. ...
Page 137
... Stops Timer1 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power managed operation ...
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... PIC18F6390/6490/8390/8490 11.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 11-1: TIMER1 BLOCK DIAGRAM ...
Page 139
... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 140
... PIC18F6390/6490/8390/8490 11.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 11-3, should be located as close as possible to the microcontroller. ...
Page 141
... RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 142
... PIC18F6390/6490/8390/8490 NOTES: DS39629B-page 140 Preliminary 2004 Microchip Technology Inc. ...
Page 143
... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... PIC18F6390/6490/8390/8490 12.2 Timer2 Interrupt Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). ...
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... Stops Timer3 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 A simplified block diagram of the Timer3 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The Timer3 module is controlled through the T3CON register (Register 13-1). It also selects the clock source options for the CCP modules (see Section 14.1.1 “ ...
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... PIC18F6390/6490/8390/8490 13.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous counter • Asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 13-1: TIMER3 BLOCK DIAGRAM ...
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... RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 13.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629B-page 146 Preliminary 2004 Microchip Technology Inc. ...
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... CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F6390/6490/8390/8490 devices have two CCP (Capture/Compare/PWM) modules, designated CCP1 and CCP2. Both modules implement standard Capture, Compare and Pulse Width Modulation (PWM) modes. REGISTER 14-1: CCPxCON REGISTER (CCP1 MODULE, CCP2 MODULE) U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ ...
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... PIC18F6390/6490/8390/8490 14.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register in turn is com- prised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
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... PWM* None Compare PWM* None PWM* Capture None PWM* Compare None PWM* PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). * Includes standard and Enhanced PWM operation. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Interaction Preliminary DS39629B-page 149 ...
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... PIC18F6390/6490/8390/8490 14.2 Capture Mode In Capture mode, the CCPR2H:CCPR2L register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the CCP2 pin (RC1 or RE7, depending on device configuration). An event is defined as one of the following: • every falling edge • every rising edge • ...
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... TMR3H TMR3L T3CCP1 Comparator CCPR2H CCPR2L 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 14.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP2M3:CCP2M0 = 1010), the CCP2 pin is not affected. Only a CCP interrupt is generated if enabled and the CCP2IE bit is set. 14.3.4 ...
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... PIC18F6390/6490/8390/8490 TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE RCON IPEN SBOREN PIR1 — ADIF PIE1 — ADIE IPR1 — ADIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP TRISC PORTC Data Direction Register ...
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... Q clock bits of the prescaler, to create the 10-bit time base. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 A PWM output (Figure 14-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
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... PIC18F6390/6490/8390/8490 14.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR2L register and to the CCP2CON<5:4> bits 10-bit resolution is available. The CCPR2L contains the eight MSbs and the CCP2CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR2L:CCP2CON<5:4>. The following equation is ...
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... Capture/Compare/PWM Register 2 (MSB) CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 3. Make the CCP2 pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629B-page 156 Preliminary 2004 Microchip Technology Inc. ...
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... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
Page 160
... PIC18F6390/6490/8390/8490 15.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
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... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 /64 OSC /16 OSC ...
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... PIC18F6390/6490/8390/8490 15.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
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... Shift Register (SSPSR) LSb MSb PROCESSOR 1 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.3.4 TYPICAL CONNECTION Figure 15-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...
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... PIC18F6390/6490/8390/8490 15.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 15- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input) ...
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... Interrupt Flag SSPSR to SSPBUF 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), ...
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... PIC18F6390/6490/8390/8490 FIGURE 15-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 15-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
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... SSPOV SSPSTAT SMP CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI Mode. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 15.3.10 BUS MODE COMPATIBILITY ...
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... PIC18F6390/6490/8390/8490 2 15 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...
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... Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 2 C™ MODE) R-0 R-0 R-0 (1) ...
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... PIC18F6390/6490/8390/8490 REGISTER 15-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 WCOL SSPOV bit 7 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I a transmission to be started (must be cleared in software collision In Slave Transmit mode: ...
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... Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive the I the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 2 C™ MODE) R/W-0 R/W-0 R/W-0 (1) (2) ...
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... PIC18F6390/6490/8390/8490 15.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I operation. Four mode selection bits (SSPCON<3:0>) 2 allow one of the following I C modes to be selected: 2 • Master mode, clock = (F /4) x (SSPADD + 1) ...
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... The clock must be released by setting bit CKP (SSPCON<4>). See Section 15.4.4 “Clock Stretching” for more detail. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F6390/6490/8390/8490 2 FIGURE 15-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39629B-page 172 Preliminary 2004 Microchip Technology Inc. ...
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... FIGURE 15-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Preliminary DS39629B-page 173 ...
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... PIC18F6390/6490/8390/8490 2 FIGURE 15-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39629B-page 174 Preliminary 2004 Microchip Technology Inc. ...
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... FIGURE 15-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Preliminary DS39629B-page 175 ...
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... PIC18F6390/6490/8390/8490 15.4.4 CLOCK STRETCHING Both 7 and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence ...
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... DX SCL CKP WR SSPCON 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 15-12) ...
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... PIC18F6390/6490/8390/8490 2 FIGURE 15-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39629B-page 178 Preliminary 2004 Microchip Technology Inc. ...
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... FIGURE 15-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Preliminary DS39629B-page 179 ...
Page 182
... PIC18F6390/6490/8390/8490 15.4.5 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the Start condition usually deter- mines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all ...
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... FIGURE 15-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condi- tion is complete ...
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... PIC18F6390/6490/8390/8490 2 15.4.6 Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
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... C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
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... PIC18F6390/6490/8390/8490 15.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the ...
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... FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the SCL line is sampled low before the SDA ...
Page 188
... PIC18F6390/6490/8390/8490 2 15.4 MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD< ...
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... WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowl- edge (ACK = 1) ...
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... PIC18F6390/6490/8390/8490 2 FIGURE 15-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39629B-page 188 Preliminary 2004 Microchip Technology Inc. ...
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... FIGURE 15-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Preliminary DS39629B-page 189 ...
Page 192
... PIC18F6390/6490/8390/8490 15.4.12 ACKNOWLEDGE SEQUENCE TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to gen- erate an Acknowledge, then the ACKDT bit should be cleared ...
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... BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.4.17 MULTI-MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...
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... PIC18F6390/6490/8390/8490 15.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the Start condition (Figure 15-26). b) SCL is sampled low before SDA is asserted low (Figure 15-27). During a Start condition, both the SDA and the SCL pins are monitored ...
Page 195
... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 Set S Set SSPIF ...
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... PIC18F6390/6490/8390/8490 15.4.17.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if low level is sampled on SDA when SCL goes from low level to high level. b) SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’. ...
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... PEN BCLIF P SSPIF 2004 Microchip Technology Inc. PIC18F6390/6490/8390/8490 The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to ‘0’. After the BRG times out, SDA is sampled ...
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... PIC18F6390/6490/8390/8490 TABLE 15-4: REGISTERS ASSOCIATED WITH I Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 — ADIF PIE1 — ADIE IPR1 — ADIP TRISC PORTC Data Direction Register SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register SSPADD Synchronous Serial Port Receive Buffer/Transmit Register ...
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... ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) PIC18F6390/6490/8390/8490 devices have three serial I/O modules: the MSSP module, discussed in the previous chapter and two Universal Synchronous Asynchronous Receiver Transmitter (USART) mod- ules. (Generically, the USART is also known as a Serial Communications Interface or SCI.) The USART can be ...
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... PIC18F6390/6490/8390/8490 REGISTER 16-1: TXSTA1: EUSART TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 CSRC bit 7 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode Master mode (clock generated internally from BRG Slave mode (clock from external source) bit 6 ...